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| daurnimator | https://fossi-foundation.org/2020/06/30/skywater-pdk | 07:13 |
|---|---|---|
| tpb | Title: Produce your own physical chips. For free. In the Open. (at fossi-foundation.org) | 07:13 |
| daurnimator | getting a bit of press on HN | 07:16 |
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| scientes | Can I use https://github.com/circt/circt with Fomu? | 10:21 |
| tpb | Title: GitHub - circt/circt: Circuit IR Compilers and Tools (at github.com) | 10:21 |
| xobs | I'm not sure what that is, but I do see references to emitting Verilog, which you could then feed to yosys. | 10:26 |
| scientes | I found this https://workshop.fomu.im/en/latest/background.html | 10:26 |
| tpb | Title: Background FPGA Tomu (Fomu) Workshop 0.1-194-g810431e documentation (at workshop.fomu.im) | 10:26 |
| scientes | I am just a software person new to FPGAs | 10:27 |
| scientes | xobs, and is there some code that shows using the USB bus? | 10:28 |
| xobs | scientes: From a software perspective, you can just use tinyusb: https://workshop.fomu.im/en/latest/riscv.html#further-risc-v-experiments | 10:29 |
| tpb | Title: Fomu as a CPU FPGA Tomu (Fomu) Workshop 0.1-194-g810431e documentation (at workshop.fomu.im) | 10:29 |
| xobs | Fomu has no external USB component -- the USB hardware is actually in the FPGA bitstream. So if you want to do something with e.g. Verilog, you need to include it in your bitstream. | 10:31 |
| xobs | If you create a module using litex, the USB core is added automatically. Manually adding it in litex looks something like: https://github.com/im-tomu/valentyusb/ | 10:32 |
| tpb | Title: GitHub - im-tomu/valentyusb: FPGA USB stack written in LiteX (at github.com) | 10:32 |
| scientes | this looks like the cheapest way to start with FPGAs | 10:33 |
| daurnimator | scientes: ah; you can update the workshop docs to add zig :) | 10:33 |
| scientes | I would kinda like something with a better bus, but given that I am on laptop, I think FOMU is the best I am going to get | 10:35 |
| xobs | What do you mean a better bus? | 10:36 |
| xobs | More I/Os? | 10:36 |
| scientes | can you view the actual generated LUT code for these things? | 10:43 |
| scientes | is that open source? | 10:43 |
| xobs | It's all open source, so yes you could view the floorplan. Most FPGA tools, even closed ones, will let you view the floorplan. `nextpnr-ice40` as it's shipped right now doesn't have Qt enabled, because Qt is hard to build and distribute. | 10:45 |
| xobs | You can probably get yosys to generate the output somehow, but I'm unclear how to exactly do that. | 10:46 |
| scientes | cool, so I can work on compiling directly to this thing | 10:46 |
| scientes | awesome | 10:46 |
| xobs | It'd be a bit like asking for disassembly of software if your cpu only had one instruction. | 10:47 |
| scientes | cause with arm/x86 you end up looking at a C machine all the time and it warps people perspective, like zig does not do strict aliasing because it was too hard on people's brains | 10:47 |
| mwfc | as to cheapest fpga solution to learn, depending on how many IOs you need, there are a couple of other boards in the price range with ICE40. the FOMU is awesome as it completely fits in your usb port | 10:47 |
| scientes | mwfc, yeah i can just stick it in my 2nd usb port of my laptop (other for mouse) | 10:49 |
| scientes | I want to try compiling parsers directly to FPGA | 10:51 |
| mwfc | neat | 10:53 |
| scientes | 16 x 16 Multiply & 32 bit Accumulator Blocks 4 8 | 10:55 |
| scientes | so you can't do much even addition or subtraction unless you want to do scheduling | 10:57 |
| xobs | You can do a ton of addition. Or subtraction. You just have to build it all up yourself. | 11:07 |
| xobs | Or rather, let the synthesizer do it for you. | 11:07 |
| scientes | can you link me to a sample floor plan | 11:08 |
| xobs | Those DSP blocks are just to save on space. You could do a 16x16 multiply in logic, but it's not cheap. I want to say on the order of 400-500 LCs. Whereas a DSP unit is just one logic element plus some glue. | 11:08 |
| scientes | that background doesn't cover routing | 11:08 |
| scientes | xobs, that is why clang is adding i3, i5 et cetera | 11:08 |
| scientes | which llvm has supported forever | 11:08 |
| xobs | I'm not sure how useful floorplanning is in the open source tools. For example, here's a floorplan in Vivado: https://forums.xilinx.com/t5/Implementation/Query-of-placed-amp-routed-IP-in-FPGA-floorplan/td-p/815078 | 11:10 |
| tpb | Title: Solved: Query of placed & routed IP in FPGA floorplan - Community Forums (at forums.xilinx.com) | 11:10 |
| xobs | nextpnr has https://camo.githubusercontent.com/55494d385a06b28afbe9dfc10c245453ac9e2a7f/68747470733a2f2f692e696d6775722e636f6d2f3073706d6c42612e706e67 in their readme. | 11:10 |
| scientes | I am just trying to understand what the hardware fundamentally is | 11:17 |
| scientes | how do these interconnects work? | 11:17 |
| xobs | If you look in the most recent picture, you can see wires connecting everything together. FPGAs, and in particular ones like the ICE40 used in Fomu, have a ton of wires connecting everything together. | 11:19 |
| scientes | oh ok, so you can basically just say this wire connects to this wire, and it figures it out | 11:19 |
| scientes | and then arranges your LUTs for you | 11:19 |
| xobs | You could do that, but it very quickly grows unwieldy. | 11:19 |
| scientes | I'm just trying to figure out what the hardware is | 11:20 |
| scientes | of course everything is automated | 11:20 |
| xobs | So in practice, unless you're doing something truly bizarre like a ring oscillator, rather than designing an adder out of Logic Cells, you say `x = y + z` and let the synthesizer build one out of LCs for you. | 11:21 |
| xobs | The fundamental LCs in the ICE40 are a 4-input LUT (which was pictured on the first link you sent). That and a ton of wires. | 11:22 |
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| scientes | "no datapath bypass" https://github.com/SpinalHDL/VexRiscv | 16:24 |
| tpb | Title: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at github.com) | 16:24 |
| scientes | what does that mean? | 16:24 |
| scientes | ahh it just means turning off some optimization | 16:25 |
| xobs | Yeah, it has to do with how the CPU pipeline works. Here's a SO response that seems to describe it well: https://stackoverflow.com/questions/40054344/pipelining-with-bypassing | 16:26 |
| tpb | Title: pipeline - Pipelining with bypassing - Stack Overflow (at stackoverflow.com) | 16:26 |
| scientes | ahh so no multiply, divide, compressed instructions | 16:28 |
| scientes | or floating point (of course) | 16:28 |
| xobs | They're currently disabled. | 16:28 |
| scientes | and a slow shift | 16:28 |
| scientes | "static branch" does that mean static branch prediction? | 16:28 |
| xobs | There was a branch that enabled multiply instructions at the expense of the debug core. | 16:28 |
| xobs | I believe static branch means it will always take the branch if it's backwards. | 16:29 |
| scientes | ok, so this is a pretty small FPGA | 16:30 |
| xobs | It is. | 16:30 |
| xobs | It's also a small FPGA. | 16:30 |
| xobs | It also has 128 kB of RAM, which is relatively rare in this size of FPGA. | 16:30 |
| scientes | and a really open toolchain | 16:31 |
| scientes | how do i install valentyusb | 18:22 |
| scientes | I am more of a C person | 18:22 |
| CarlFK | scientes: have you done the workshop tutorial? (you can do it on your own in a few hours, ask here for help if you get stuck) | 18:25 |
| scientes | CarlFK, well I don't have the Fomu so i have to build it and get verilog to use verilator | 18:26 |
| CarlFK | where are you located? | 18:27 |
| CarlFK | given your interest in this stuff, you should have one. | 18:28 |
| scientes | yeah I will get one in a bit | 18:28 |
| scientes | I am in Georgia, the country | 18:28 |
| scientes | but I am from the US | 18:29 |
| CarlFK | heh - I read Georgia on the country | 18:30 |
| CarlFK | er, in, not on. | 18:30 |
| CarlFK | heh - I read Georgia in the country | 18:30 |
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