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| leons | Pretty new to Fomu here. I'm trying to build a Verilog device running on Fomu and somehow establishing a serial communication link to my Linux PC. What would be the "best" / easiest way to do this? Etherbone? | 17:03 |
|---|---|---|
| tnt | etherbone is ... ethernet ? | 17:04 |
| leons | I have some (very theoretical) background in FPGA but no practical experience - written a lot of VHDL, but only ever simulated, never seen the magic happen. Want to get it off the ground with Fomu | 17:05 |
| leons | I thought I could use etherbone to interface with wishbone from applications? | 17:05 |
| tnt | So the fomu doesn't have any hw expect the fpga, which mean to make it appear as a "serial device" to the pc, you need a USB core and either logic or software running on a softcore driving that usb core to respond appropriately to all the usb specificiation requests and implement the CDC specification. | 17:08 |
| tnt | s/expect/except/ | 17:08 |
| tnt | So as a starting point you can use the default fomu soc which has a riscv core and a usb controller there and modify the software and gateware to pipe data to some custom core you'd add to it off a wishbone bus. | 17:10 |
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| tnt | I know Greg Davill also made a fully hardware version that implement cdc without a softcore, maybe check his github, not sure what the state of it. Also this was tested on ecp5 which is way faster than a up5k so no idea if his implementation meets timing at all on there. | 17:12 |
| leons | That's what I thought. As far as I know the USB is implemented with the RISC-V Softcore, right? I was thinking about having my verilog run as just another device on the wishbone bus | 17:12 |
| leons | I was kind of hoping I could use the Wishbone USB bridge without the accompanying softcore and just have my custom core on the bus, along with the bridge | 17:15 |
| tnt | the usb is implemented like on a classic microcontroller with usb. You have some usb dedicated logic that handles the lower level of USB but the higher level part of the stack is run on the riscv. | 17:15 |
| tnt | I know xobs also implemented a "dummy" version that just enumerated, that might be enough for the wishbone bridge to work, I have no clue, never looked into that. | 17:17 |
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| leons | Oh, I think the litex/workshop_rgb.py does exactly what I want to do! How could I've missed that... Now to figure out how to use Verilog instead of migen | 17:22 |
| tnt | you'll probably still have to use litex/migen to the "top level", but you can tell it to manually add verilog file to the build list and then use a Instance(...) to manually instanciate your verilog logic in the litex topleve. | 17:24 |
| leons | That would've been my next step :) Thanks for the help, this is all pretty new for me | 17:25 |
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| leons | tnt: After reading over documentation and some LiteX code I still can't figure out how to introduce my verilog into the build process (` | 18:50 |
| leons | \csrecho' is not part of the design. Do you have a hint here? | 18:50 |
| tnt | not really sorry ... I don't actually use litex, I only know its "high level architecture". | 18:53 |
| tnt | The VexRISCV cpu used in it is actually a verilog core (well ... a spinalhdl core really but generated the verilog for inclusion in litex) so maybe you can look how they did that as an example ? | 18:54 |
| ovf | this is some glue around tinyfpga's usbserial that gets it running on fomu, including the rgb demo: https://github.com/stef/nb-fomu-hw | 18:55 |
| tpb | Title: GitHub - stef/nb-fomu-hw: non-blinky fomu hello world (fpga usb uart demos) (at github.com) | 18:55 |
| tnt | That's really not a great code / example to reproduce ... | 18:57 |
| tnt | it missed timing by like 30% | 18:57 |
| tnt | and AFAIR violates several parts of the usb specification. | 18:57 |
| ovf | indeed, it would be nice to have an improvement on that which would share the property of not having a lot of magic (i.e. the complete verilog source for that one is <2kloc) | 18:59 |
| tnt | yeah, adding a standalone mode to my usb core to get easy usb -> fifos interface is on my TODO list ... | 19:02 |
| leons | tnt: soc.platform.add_source did the trick! :) | 19:10 |
| tnt | leons: :) | 19:31 |
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