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| xobs | I couldn't fit in privilege level stuff such as exception and interrupt delegation or atomic instructions. You could do it, but the emulator layer would be rather large. | 00:03 |
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| tnt | xobs: but those are handled in sw emulation anyway right they're not in HW in the Vex ? | 07:43 |
| daveshah | Atomics are mostly emulated, there might be some hardware support in the cache too | 07:45 |
| xobs | tnt: they can be, depending on the configuration. For example, the linux CSR plugin has things like stvec, sepc, scause, medeleg, and mideleg: https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L85-L122 | 07:46 |
| tpb | Title: VexRiscv/CsrPlugin.scala at master · SpinalHDL/VexRiscv · GitHub (at github.com) | 07:46 |
| xobs | The only thing Fomu has is satp. But the rest can be emulated. | 07:46 |
| tnt | xobs: Where can I find the scala core config you used ? | 07:47 |
| xobs | tnt: https://github.com/xobs/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenFomu.scala | 07:47 |
| tpb | Title: VexRiscv-verilog/GenFomu.scala at master · xobs/VexRiscv-verilog · GitHub (at github.com) | 07:47 |
| tnt | tx ! | 07:48 |
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