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| st-gourichon-fid | Mmh... FOMU Hacker with default (bootloader) softcore CPU. I managed to get all code and read-only data to RAM to check for performance. I get a 7 times speedup for a "computation-intensive" (matrix multiplication) when all code is in RAM, compared to when all code is in Flash. | 16:14 |
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| st-gourichon-fid | The trick is (1) not to put all sections in RAM because the bootloader just jumps to flash 0x20040000, rather in linker.ld redirect all input sections to the .data output section, except .text.start section. | 16:15 |
| st-gourichon-fid | and (2) change crt0 so that all init code is in section .text.start (else only the first jump is there, a relative one that cannot reach to RAM because too far, yielding a relocation error)/ | 16:16 |
| st-gourichon-fid | *Big surprise*: first I moved all my code but not the most-called __mulsi3 to RAM, and my computation went from 1200 to 163 milliseconds. So far so good. I expected moving all code including __mulsi3 to RAM would yield another boost. After all it's the innermost loop. But no. Mostly same performance. Question. Is there some kind of minuscule cache (like 1 page) between CPU and Flash in the default softcore of foboot? | 16:20 |
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| acathla | Where can I buy an evaluation board supported by litex, with an ECP5? Like the orangecrab or the TinyFPGA-EX... | 17:11 |
| acathla | daveshah, where can I get a trellis board? | 17:17 |
| daveshah | acathla: they aren't commercially available | 17:18 |
| daveshah | Your best bet is a Lattice Versa or EVN | 17:18 |
| acathla | Ok, I just saw the Versa is available. | 17:18 |
| acathla | And also the EVN, directly on their website. | 17:25 |
| daveshah | Note that the EVN doesn't have any external DRAM | 17:26 |
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| mithro | acathla: It seems like the Colorlight board will soon be the cheapest option but its not really *designed* to be a dev board | 17:50 |
| mithro | acathla: https://github.com/q3k/chubby75/blob/master/5a-75b/README.md | 17:51 |
| tpb | Title: chubby75/README.md at master · q3k/chubby75 · GitHub (at github.com) | 17:51 |
| mithro | st-gourichon-fid: We need to move the SPI controller into it's own clock domain and run it much faster than the CPU | 17:51 |
| acathla | mithro, is it in production somewhere? | 17:52 |
| mithro | acathla: It's available from Aliexpress for like $15 USD | 17:52 |
| mithro | st-gourichon-fid: The Fomu has about 8kbyte of cache | 17:52 |
| st-gourichon-fid | mithro, thanks for the update. | 17:52 |
| mithro | st-gourichon-fid: Might only be 4kbytes -- unsure how xobs has configured it | 17:53 |
| mithro | but there is a small cache | 17:53 |
| st-gourichon-fid | mithro, thanks. I guess the answer is somewhere within https://github.com/im-tomu/foboot/tree/master/hw | 17:54 |
| tpb | Title: foboot/hw at master · im-tomu/foboot · GitHub (at github.com) | 17:54 |
| mithro | st-gourichon-fid: Probably from https://github.com/im-tomu/foboot/blob/master/hw/foboot-bitstream.py#L139 | 17:55 |
| tpb | Title: foboot/foboot-bitstream.py at master · im-tomu/foboot · GitHub (at github.com) | 17:55 |
| mithro | https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L183 | 17:56 |
| tpb | Title: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com) | 17:57 |
| mithro | which goes to https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py | 17:58 |
| tpb | Title: litex/core.py at master · enjoy-digital/litex · GitHub (at github.com) | 17:58 |
| mithro | st-gourichon-fid: Which ends up at https://github.com/enjoy-digital/VexRiscv-verilog/blob/854f9bd2282c97251ce65e4117c5cf1630722004/VexRiscv_Lite.yaml probably? | 18:03 |
| tpb | Title: VexRiscv-verilog/VexRiscv_Lite.yaml at 854f9bd2282c97251ce65e4117c5cf1630722004 · enjoy-digital/VexRiscv-verilog · GitHub (at github.com) | 18:03 |
| mithro | st-gourichon-fid: vexriscv.CacheReport {bytePerLine: 32, size: 2048} | 18:04 |
| st-gourichon-fid | So, 2kb cache with 32-byte lines I guess. | 18:04 |
| st-gourichon-fid | mithro, does it explain/confirm that, in practice, if the inner loop of a code depends on a little part of the flash (like, __mulsi3), we get nearly the same performance as with pure RAM (when loop count is very high). | 18:04 |
| st-gourichon-fid | ? | 18:04 |
| mithro | st-gourichon-fid: Yeah | 18:05 |
| st-gourichon-fid | Thanks a lot mithro! This kind of hint will help me explore, understand and customize the design for our project. | 18:06 |
| mithro | st-gourichon-fid: I think you could probably do a single cycle hardware multiply using the DSP | 18:06 |
| mithro | s/DSP/DSP blocks/ | 18:06 |
| mithro | st-gourichon-fid: There is a lot of room for optimization work here too | 18:06 |
| st-gourichon-fid | Any reference to a project that does that? Or at least goes into that direction. | 18:07 |
| acathla | Someone did it on the ICE40 recently if I remember correctly... | 18:07 |
| mithro | st-gourichon-fid: Like you could probably store the cache table in the block RAM while the cache contents in the SP-RAM for a much bigger cache | 18:07 |
| mithro | st-gourichon-fid: Problem is the debug controller doesn't fit | 18:07 |
| mithro | st-gourichon-fid: xobs has something somewhere... | 18:08 |
| st-gourichon-fid | We are searching for accelerated multiply using "hmul" "ice40" in Google. | 18:08 |
| mithro | st-gourichon-fid: https://github.com/SpinalHDL/VexRiscv/issues/40 | 18:08 |
| tpb | Title: Add support for using the DSP blocks on the iCE40UP5K? · Issue #40 · SpinalHDL/VexRiscv · GitHub (at github.com) | 18:08 |
| st-gourichon-fid | mithro, bingo highly relevant github issue. | 18:09 |
| mithro | st-gourichon-fid: https://github.com/im-tomu/fomu-tests/tree/master/mul-infer | 18:09 |
| tpb | Title: fomu-tests/mul-infer at master · im-tomu/fomu-tests · GitHub (at github.com) | 18:09 |
| mithro | Oh interesting -> https://github.com/tomverbeure/VexRiscv/commit/ae85698a2bf674e99c744169e56f8cbf2874778a | 18:10 |
| tpb | Title: MulSimple · tomverbeure/VexRiscv@ae85698 · GitHub (at github.com) | 18:10 |
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| st-gourichon-fid | Interesting. I take note of all this. | 18:48 |
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| sdfsfsfsdfsdfsf | hi, the fomu.im site says it can be a u2f like the tomu.im.... anyone know where that code is on the github? | 18:59 |
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| st-gourichon-fid | mithro, I see that the commit you mention is included in master branch of https://github.com/SpinalHDL/VexRiscv | 20:16 |
| tpb | Title: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at github.com) | 20:16 |
| st-gourichon-fid | git branch -a --contains ae85698a2bf674e99c744169e56f8cbf2874778a | grep -i SpinalHDL | 20:18 |
| st-gourichon-fid | Merged in https://github.com/SpinalHDL/VexRiscv/commit/46f10bacb212e763a4b97414cd747447bea368f2 | 20:21 |
| tpb | Title: Merge pull request #64 from tomverbeure/MulSimple · SpinalHDL/VexRiscv@46f10ba · GitHub (at github.com) | 20:21 |
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| st-gourichon-fid | sdfsfsfsdfsdfsf has already quit, but it looks like Google knows answers, like https://github.com/im-tomu/tomu-samples/issues/3 | 21:11 |
| tpb | Title: Create a FIDO / U2F compatible firmware · Issue #3 · im-tomu/tomu-samples · GitHub (at github.com) | 21:11 |
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| pollo | that's for the tomu | 21:14 |
| CarlFK | st-gourichon-fid: I think they wanted something for fomu | 21:14 |
| CarlFK | yes, that. | 21:14 |
| pollo | someone here worked on that though | 21:17 |
| * pollo checks his IRC logs | 21:18 | |
| pollo | that was vesim :) | 21:19 |
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