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| mithro | MadHacker: How much space does the 6502 take? | 14:44 |
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| MadHacker | mithro: https://paste.debian.net/1093204/ - 907 out of 1280 LC's with a bit of ROM and RAM stuffed into the BRAM, using arachepnr. | 15:21 |
| tpb | Title: debian Pastezone (at paste.debian.net) | 15:21 |
| MadHacker | That's basically just the 6502 itself, 512 bytes of RAM at 0x0000, 256 bytes of ROM at 0xFF00, and a 4-bit LED register at 0xFE60, and the decoding of those addresses. | 15:22 |
| xobs | MadHacker: could port basic to Fomu nicely... | 15:22 |
| MadHacker | xobs: Trivially! | 15:22 |
| MadHacker | That's not my own 6502 core, BTW, that's the arlet one. | 15:22 |
| MadHacker | https://github.com/Arlet/verilog-6502 | 15:23 |
| tpb | Title: GitHub - Arlet/verilog-6502: A Verilog HDL model of the MOS 6502 CPU (at github.com) | 15:23 |
| MadHacker | Works well though, and it's completely trivial to get running. | 15:23 |
| mithro | Why would you use arachnepnr? | 15:23 |
| MadHacker | It was just handy. This was a build on a Pi where I just ran that icetools.sh and hadn't gotten around to building nextpnr yet. | 15:24 |
| MadHacker | My fomu EVT order hasn't shipped yet, so the iCEblink ice40HX1K is all I had handy. | 15:25 |
| MadHacker | Well, outside my HX8K boards for the novena. | 15:25 |
| MadHacker | I wanted this on a Pi for other reasons (mechanical size stuff) | 15:25 |
| MadHacker | 6502's the one CPU I know well enough to not need an assembler to build a boot ROM to test, and to be able to read the address+data buses directly and understand what's going on reliably. | 15:26 |
| MadHacker | 26-bit ARM I might do OK too, I guess. | 15:26 |
| MadHacker | Give me a little while, I'll set up nextpnr and give it a go. | 15:31 |
| mithro | xobs: I thought all the EVT boards had shipped? | 15:42 |
| MadHacker | It was a late order. Only placed it on the 13th. | 15:44 |
| MadHacker | From the website: Originally expected to ship on Jul 30, 2019 | 15:44 |
| MadHacker | Currently expected to ship on Aug 02, 2019 | 15:44 |
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| ovf | xobs: 6502 would fit together with usbuart, right? | 15:58 |
| xobs | ovf: I don't have a usbuart yet, but I should be able to adapt dummyusb to present a uart to the device. | 15:59 |
| MadHacker | I suspect there are more compact 6502 cores out there. Dropping BCD mode would simplify things a bit, for example, and it's not heavily used. | 16:00 |
| MadHacker | But it's already pretty small. | 16:00 |
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| MadHacker | mithro: NextPNR gives ICESTORM_LC: 879/ 1280 | 16:09 |
| MadHacker | (same logic) | 16:09 |
| MadHacker | nextpnr not the weird capitalisation, sorry. :) | 16:09 |
| xobs | MadHacker: what if you add "-relut" to "synth_ice40" in yosys? | 16:09 |
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| MadHacker | No changes, assuming it didn't need any further options. | 16:12 |
| xobs | The options we use for Fomu are "synth_ice40 -top top -json top.json -relut -dffe_min_ce_use 4 -dsp" | 16:12 |
| xobs | Still, that's delightfully small. | 16:13 |
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| MadHacker | The HX1K has no DSP slices so that bit doesn't work. The dffe_min_ce_use actually makes it slightly worse on this design. | 16:37 |
| MadHacker | (917 LCs) | 16:37 |
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| tnt | Someone had a 6502 running the commodore basic on an icebreaker. | 18:06 |
| tnt | emeb: that was you right ? | 18:06 |
| emeb | tnt: Xark took my 6502 design and ported it to icebreaker. | 18:07 |
| emeb | https://github.com/XarkLabs/up5k_vga/tree/master/demos | 18:08 |
| tpb | Title: up5k_vga/demos at master · XarkLabs/up5k_vga · GitHub (at github.com) | 18:08 |
| tnt | emeb: oh yeah right, you were on a up5k but a custom board. | 18:08 |
| emeb | tnt: correct | 18:09 |
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| mithro | 900 LCs seems a lot for an 8bit CPU..... | 20:06 |
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| tnt | mithro: well it's also not a 8-bit cpu that was ever designed to map to fpga 4-lut architecture. | 20:11 |
| mithro | tnt: Yeah, true | 20:14 |
| mithro | tnt: And if you want to make your life miserable, might as well go all the way ;-) | 20:14 |
| tnt | :) I'm not sure if that code is also designed to emultate the 6502 accurately since alot of 6502 sw tends to use "non-documented" features and so emulating bad opcodes and exact timings is often needed. | 20:15 |
| tnt | I wrote a 16-bit cpu specificaly for the iCE40 and could only get it down to 600 LCs. | 20:15 |
| emeb | and fwiw there's a 65C02 out there, derived from Arlet's. Not much bigger and the extra instructions are helpful: https://github.com/hoglet67/verilog-6502 | 20:18 |
| tpb | Title: GitHub - hoglet67/verilog-6502: A Verilog HDL model of the MOS 6502 CPU (at github.com) | 20:18 |
| emeb | but it's true - these 8-bit cores are definitely *not* tuned for FPGA implementation. Compared to stuff like picorv32 they run substantially slower. | 20:20 |
| emeb | (clock rates) | 20:21 |
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| MadHacker | Be interesting to play with one that is, and see if it can emulate a fatter CPU in a smaller number of gates. | 20:47 |
| MadHacker | e.g. a bit-sliced implementation of risc-v. | 20:48 |
| tnt | Well someone made a native bitsliced riscv :p | 20:52 |
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| mithro | tnt: Any idea what resource usage boneless is at these days? | 21:50 |
| tnt | mithro: About the same range at the latest news. | 21:51 |
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