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| mithro | xobs: https://github.com/enjoy-digital/litex/pull/175/files | 00:10 |
|---|---|---|
| tpb | Title: Standardizing `cpu_variants` and adding lots of documentation by mithro · Pull Request #175 · enjoy-digital/litex · GitHub (at github.com) | 00:10 |
| xobs | mithro: that looks like a refreshing standardization of the default options! | 01:42 |
| xobs | vexriscv has the option to add "c" instructions too, by the way. I don't know how important that is. | 01:42 |
| mithro | xobs: I also added some info about compatible firmware options. | 01:43 |
| mithro | With some recommendations on when to use each type of firmware. | 01:43 |
| xobs | That's a good idea. | 01:47 |
| xobs | Note that for Fomu, we're using an external vexriscv CPU, because I'm still doing experiments. | 01:48 |
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| xobs | Hmm... My Windows machine is having all sorts of issues enumerating this device. I wonder what's going wrong. | 10:27 |
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| synaption[m] | hi! I have a bag of fomus without bootloaders. I'm trying to use fomu-pi-gen, but that just failed to build the image. I was wondering if someone had a prebuilt image or knows what I should do about this error: | 22:43 |
| synaption[m] | losetup: /pi-gen/work/2019-04-27-Fomu-Dev/export-image/-v1.2.8-fomu.img: failed to set up loop device: No such file or directory | 22:44 |
| kerel | synaption[m]: The pre-built images are part of the releases at https://github.com/im-tomu/fomu-pi-gen/releases | 22:52 |
| tpb | Title: Releases · im-tomu/fomu-pi-gen · GitHub (at github.com) | 22:52 |
| kerel | The Fomu-Dev-*-fomu.zip file seems to contain the image. | 22:53 |
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| synaption[m] | thanks! looks promising | 22:56 |
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| futarisIRCcloud | xobs / mithro: "c" instructions are important on vexriscv, if you are flash / memory constrained. Something is broken in the decoder, so it's been disabled for linux, at the moment. | 23:06 |
| futarisIRCcloud | It's RISC-V's equivalent of ARM's Thumb-2. | 23:06 |
| futarisIRCcloud | synaption[m] : The images should work any Raspberry Pi. I used a Raspberry Pi (1) and it worked fine. | 23:08 |
| tnt | how many cycles does it take the vex to execute instructions ? | 23:09 |
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| futarisIRCcloud | https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CPU-A-New-Way-To-Design.html | 23:23 |
| tpb | Title: The VexRiscV CPU - A New Way to Design | Electronics etc… (at tomverbeure.github.io) | 23:23 |
| futarisIRCcloud | If we want smaller code-size, perhaps we need to run a Z80 or 6502. | 23:24 |
| futarisIRCcloud | https://github.com/abnoname/iceZ0mb1e | 23:24 |
| tpb | Title: GitHub - abnoname/iceZ0mb1e: FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC (at github.com) | 23:24 |
| futarisIRCcloud | https://github.com/emeb/up5k_basic | 23:24 |
| tpb | Title: GitHub - emeb/up5k_basic: A small 6502 system with MS BASIC in ROM (at github.com) | 23:24 |
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