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| -_whitenotifier- [nextpnr] pull[bot] opened pull request #186: [pull] master from YosysHQ:master - https://git.io/JtRXh | 11:31 | |
| -_whitenotifier- [nextpnr] pull[bot] closed pull request #186: [pull] master from YosysHQ:master - https://git.io/JtRXh | 12:28 | |
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| orchidea | Hi, I saw that you project has a jpeg encoder. I was wondering if such entity can be extracted from the project and used without soft CPU? I'm searching an FPGA jpg encoder with no luck (only academic literature without real code) and this was the only only project with accessible vhdl code. | 13:03 |
|---|---|---|
| orchidea | (I've found only academic literature *) | 13:04 |
| orchidea | ( *I've found only academic literature) | 13:04 |
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| -_whitenotifier- [litex-buildenv] mateusz-holenko commented on issue #632: Bootstrap script fails to build python netifaces - https://git.io/JtRFv | 14:15 | |
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| -_whitenotifier- [litex-buildenv] nickoe opened issue #637: basys3 openocd config not found - https://git.io/Jt0sX | 19:52 | |
| -_whitenotifier- [litex-buildenv] nickoe opened issue #638: basys3 flterm unable to open kernel image, no such file or dir - https://git.io/Jt0GV | 20:06 | |
| -_whitenotifier- [litex-buildenv] nickoe edited issue #637: basys3 openocd config not found - https://git.io/Jt0sX | 20:06 | |
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