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| -_whitenotifier-f- [yosys] pull[bot] closed pull request #594: [pull] master from YosysHQ:master - https://git.io/JkvYF | 00:02 | |
| -_whitenotifier-f- [yosys] pull[bot] opened pull request #595: [pull] master from YosysHQ:master - https://git.io/Jkvw3 | 03:02 | |
| -_whitenotifier-f- [yosys] pull[bot] closed pull request #595: [pull] master from YosysHQ:master - https://git.io/Jkvw3 | 03:02 | |
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| Shari2 | Hi. I am currently evaluating daisho USB IP core on the Numato Opsis. I considering an upgrade of my hardware to a NeTV2. In the NeTV2 mainboard schematic the USB2.0 signals are routed directly to the FPGA. No ULPI/UTMI phy. Does that mean there is no USB 2.0 High-speed support on the NeTV2? | 16:03 |
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| CarlFK | xobs: mithro ^^^ | 19:16 |
| mithro | @Shari2 Not sure, #litex and #nmigen would probably be helpful. I would recommend using the new LUNA core rather than Daisho core these days | 19:21 |
| mithro | ktemkin is frequently around #nmigen and she wrote the LUNA core - https://luna.readthedocs.io/en/latest/ | 19:22 |
| tpb | Title: LUNA: USB Multitool and Gateware Library LUNA documentation (at luna.readthedocs.io) | 19:22 |
| Shari2 | @mithro I cloned luna repository and got the python prerequisites installed. Can I instruct nmigen to just generate the verilog code and stop? | 21:00 |
| mithro | @Shari2 I'm the wrong person to ask, try the documentation and maybe #nmigen | 21:01 |
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| Shari2 | My python is really bad, but I found that the luna core uses fullspeed for the usb2 port of the netv2. I guess that means no high-speed support without external phy because the FPGA IOs can not generate the high-speed signals. | 23:15 |
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