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| * pollo building the v4l2 bitstream for the netv2 | 04:02 | |
| pollo | mainly wanted to complain about the vivado install process :p | 04:03 |
|---|---|---|
| pollo | "'/opt/netv2/build/gateware/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu Oct 8 00:05:03 2020" | 04:06 |
| pollo | eww ? Can I disable that kind of telemetry ? | 04:06 |
| pollo | "WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license." | 04:06 |
| pollo | sigh | 04:07 |
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| pollo | hmm, I'm clearly not very experienced with FPGAs. Could someone tell me what is the difference between "loading" a bitstream and "flashing" a bitstream ? | 04:22 |
| pollo | it seems those are two different things in OpenOCD https://github.com/antmicro/netv2/blob/v4l2/netv2.py#L317 | 04:23 |
| tpb | Title: netv2/netv2.py at v4l2 · antmicro/netv2 · GitHub (at github.com) | 04:23 |
| shenki | pollo: loading programs the FPGA with your bitstream, but it goes away when the FPGA is reset or loses power | 04:47 |
| pollo | oh | 04:48 |
| shenki | pollo: flashing places the bistream in a SPI NOR flash chip | 04:48 |
| shenki | next time the FPGA starts, it will read the flash chip and program itself | 04:48 |
| pollo | I wonder why the instructions in https://github.com/antmicro/netv2/blob/v4l2/Makefile don't say to flash the bitstream then | 04:49 |
| tpb | Title: netv2/Makefile at v4l2 · antmicro/netv2 · GitHub (at github.com) | 04:49 |
| pollo | kgugala_: ^^ ? | 04:49 |
| pollo | at least, I don't plan on loading the bitstream each and everytime my computer reboots :) | 04:49 |
| shenki | when doing development it is common to only 'load' | 04:50 |
| pollo | is there any danger of bricking the board when loading a bitstream? | 04:50 |
| pollo | (in general) | 04:50 |
| pollo | anyway, enough for me for tonight, I built the bitstream and that's a win | 04:53 |
| shenki | in general, no. I have not used the netv2 so I may be wrong in the case of that board | 04:54 |
| pollo | CarlFK[m]: I'm documenting the process step by step in a lengthy blog post btw. Should be useful | 04:54 |
| pollo | obviously still a WIP, but atm it looks like this: https://veronneau.org/drafts/using-the-netv2-as-an-open-hardware-free-software-hdmi-capture-card.html | 05:08 |
| tpb | Title: Louis-Philippe Véronneau - Using the NeTV2 as an Open Hardware, Free Software HDMI capture card (at veronneau.org) | 05:08 |
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| kgugala_ | pollo: there is gateware/load target in the Makefile. It assumes you're using FTDI based JTAG adapter for programming | 06:37 |
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| pollo | kgugala: yes, my question was why load and not flash | 14:55 |
| kgugala | pollo: loading into FPGA RAM is generally much faster than flashing. the Makefile you referring to is used in development so there is no point to flash the bitstream every iteration | 15:23 |
| pollo | Thanks for the precision. I'll try flashing the bitstream once I confirm I can load it properly then | 15:25 |
| pollo | As I want to use the board in production :) | 15:25 |
| kgugala | sure, you still may need to force pcie rescan (if your PC boots faster than the FPGA configures itself from flash) | 15:33 |
| pollo | noted, thanks for the tip | 15:37 |
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| -_whitenotifier-f- [yosys] pull[bot] opened pull request #570: [pull] master from YosysHQ:master - https://git.io/JUjbt | 19:05 | |
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