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| CarlFK | @CarlFK I'm not an IRC user so I'm not sure how to find the video you mentioned, but I'll likely go for one of these (or similar): https://sigrok.org/wiki/Mcupro_Logic16_clone | 03:59 |
|---|---|---|
| tpb | Title: mcupro Logic16 clone - sigrok (at sigrok.org) | 03:59 |
| CarlFK | <- protocol bridge | 03:59 |
| mithro | CarlFK: Pipistrello with the Logic board is a good choice for capturing USB | 04:34 |
| mithro | This is what I have been using to capture the ValentyUSB traces -> https://sigrok.org/wiki/Saanlima_Pipistrello_OLS | 04:34 |
| tpb | Title: Saanlima Pipistrello OLS - sigrok (at sigrok.org) | 04:34 |
| mithro | Anyway, home time for me... | 04:35 |
| CarlFK | mithro: | 04:35 |
| CarlFK | bring Opsis board for show n tell | 04:35 |
| CarlFK | I have enough for recording, but not for a bare bord | 04:35 |
| xobs | Speaking of USB captures, pyusb is being weird. It's not sending IN packets sometimes. | 04:59 |
| xobs | For example: | 04:59 |
| * xobs uploaded an image: image.png (92KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/QegaISCsAykwYSqVVMIeuujV > | 04:59 | |
| xobs | It sent a SETUP packet, followed by an OUT packet. Both were responded to. Then it decided to send the SETUP packet again. | 05:00 |
| xobs | I suppose I could add a counter, and not redo duplicated writes like that. But I'd really like to know why pyusb is doing that. | 05:02 |
| CarlFK | thaytan: speed was the problem!!! | 05:17 |
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| xobs | Oh. Wow... Apparently that's legal. I thought a SETUP packet had to be followed by an IN packet on the same endpoint. But apparently that's not the case. | 05:49 |
| * xobs uploaded an image: image.png (138KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/LfHtEAKSGpWsNDYLJQyrzItr > | 05:49 | |
| xobs | SETUP0, IN1, IN0, OUT0. This'll require some changes. | 05:50 |
| thaytan | CarlFK[m], glad you figured it out! | 06:06 |
| CarlFK[m] | I had to hook up a logic analyzer and see that the python code wasn't being interpreted as valid spi signals | 06:07 |
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| xobs | Okay, I managed to fix the debugger. I'm still having other issues, but micropython is definitely allocating memory incorrectly. It tried to print a string whose address was the same as my USB management pointers. I think the heap isn't behaving as it should. | 08:26 |
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| xobs | And this is cool. I can tell that it's failing in mp_map_lookup() because it's doing an unaligned access. | 10:52 |
| xobs | MicroPython v1.10-291-gdd7d522-dirty on 2019-04-23; fomu with vexriscv | 11:43 |
| cr1901_modern | doesn't riscv support unaligned access? | 11:44 |
| daveshah | It's optional | 11:44 |
| xobs | cr1901_modern: it does! kinda. it raises an exception. | 11:44 |
| daveshah | on most implementations it causes a trap | 11:44 |
| xobs | so if it doesn't support it, it causes a trap, but you have everything you need to handle it in software. | 11:44 |
| xobs | However, the real problem was due to hardware support. | 11:44 |
| cr1901_modern | daveshah: Not to be pedantic (oh who am I kidding), but I included traps under "impls are required to handle it" | 11:45 |
| xobs | This is an RV32I core, which has no MUL/DIV. I was using the wrong ABI, but weirdly the vexriscv will kinda attempt to execute a "divu" instruction. Which corrupted the heap address, putting it in some strange offset. | 11:45 |
| cr1901_modern | I remember complaining a decent amount that having to support unaligned access makes space sensitive impls annoying | 11:45 |
| xobs | Which caused the allocator to freak out. | 11:45 |
| xobs | Which caused unalligned accesses. | 11:45 |
| cr1901_modern | (in my "riscv on ice40hx1k core", if I ever finish it, unaligned accesses will be microcoded) | 11:46 |
| daveshah | That's definitely not compliant, it should be causing an illegal instruction tra | 11:46 |
| daveshah | *trap | 11:46 |
| xobs | A trap would have made diagnosing this a lot easier. | 11:54 |
| xobs | On the bright side, I got to take the usb debugger for a spin. | 11:54 |
| cr1901_modern | is that tnt's debugger or your own? | 11:57 |
| xobs | It's gdb, running over openocd, connecting to the litex wishbone bridge, tunnelling over usb, connecting to the debug port on the vexriscv. | 12:04 |
| cr1901_modern | Sorry I asked | 12:05 |
| xobs | I feel the need to combine various sections of that sculpture. | 12:06 |
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| xobs | That makes sense -- I disabled illegal instruction traps to shrink the core down. Duh. | 15:20 |
| xobs | When I re-enable it the LC utilization goes to 100%, and naturally it won't route anymore. | 15:20 |
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