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| xobs | Did something change with CSRs? I'm trying to use one in my design, and I'm getting an error that `'CSR' object has no attribute 'get_fragment_called'` which is true since it doesn't inherit from Module. | 05:15 |
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| CarlFK | what's a CSR? | 05:29 |
| CarlFK | Client Service Rep :p | 05:29 |
| xobs | CarlFK: Configuration and Status Register | 05:29 |
| CarlFK | what crashed: http://paste.ubuntu.com/p/k5KVYzZFQk/ | 05:29 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 05:29 |
| CarlFK | I launched /home/juser/tv/litex-buildenv/./scripts/build-qemu.sh and 100 things happen | 05:30 |
| xobs | Oh, I guess maybe CSRs aren't actually submodules, so they shouldn't be added with `self.submodules = ...` | 05:37 |
| mithro | xobs: That is complicated | 05:38 |
| mithro | xobs: If they want to simulate properly they need to be submodules... | 05:39 |
| xobs | mithro: but if you want to synthesize at all, they need to not be submodules. | 05:39 |
| mithro | xobs: See the random fixes in my litex / migen branches -- I haven't had time to figure out if they are /right/ yet | 05:42 |
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| xobs | mithro: Is that why tests give me the error "TypeError: do_finalize() missing 1 required positional argument: 'busword'"? | 06:02 |
| mithro | xobs: Yes - that means you don't have my patch | 06:03 |
| mithro | s/patch/hack/ | 06:03 |
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| xobs | mithro: What's the long-term solution? | 06:09 |
| mithro | xobs: Figure out what the correct solution and get that upstream? :-P | 06:09 |
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| mithro | xobs: I think the first thing is to chat to _florent_ and whitequark | 06:33 |
| mithro | I'm pretty sure I logged a bug somewhere... | 06:33 |
| mithro | I believe I was pretty clear in the commit messages somewhere... | 06:34 |
| xobs | mithro: does anyone else use simulation? This seems like the sort of thing that's either really broken, or we're doing it wrong. | 06:43 |
| mithro | xobs: Not for anything big | 06:43 |
| xobs | I also noticed that migen throws confusing depreciation warnings under python 3.7. | 06:45 |
| xobs | I'll talk to _florent_ | 06:46 |
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| _florent_ | xobs: hi, i can try to help, can you share your code? from what i understand if was working before but it's no longer the case? | 08:46 |
| xobs | _florent_: I'm working on simplifying the valentyusb stuff mithro did in order to demonstrate the problem. mithro mentions that CSRs aren't properly simulated unless they're instantiated as submodules. | 08:48 |
| _florent_ | xobs: ok, i'm going to look at that | 08:56 |
| xobs | _florent_: Sorry I'm not able to give a more articulate answer -- I'm still trying to understand how it's all supposed to work. | 08:59 |
| _florent_ | xobs: i don't think we need to declare CSR as submodules | 09:00 |
| _florent_ | xobs: from the simulation, CSRs are just group of signals: re and storage for CSRStorage, re and status for a CSRStatus, etc... | 09:00 |
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| xobs | _florent_: One problem I'm definitely having is that migen's fhdl says "TypeError: do_finalize() missing 1 required positional argument: 'busword'" | 09:01 |
| _florent_ | xobs: can you give me a link of what you are testing? or the code? | 09:02 |
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| xobs | _florent_: the most well-tested module is https://github.com/xobs/valentyusb/blob/xobs-usb12/valentyusb/usbcore/cpu/epfifo.py (the test driver is at https://github.com/xobs/valentyusb/blob/xobs-usb12/valentyusb/usbcore/cpu/epfifo_test.py with an example test at https://github.com/xobs/valentyusb/blob/xobs-usb12/valentyusb/usbcore/test/common.py#L424) | 09:08 |
| tpb | Title: valentyusb/epfifo.py at xobs-usb12 · xobs/valentyusb · GitHub (at github.com) | 09:08 |
| xobs | It's somewhat large and baroque, so I'm working on a smaller testcase. | 09:08 |
| xobs | _florent_: https://gist.github.com/xobs/69bcf5b947926da89171c10ac7aff58e (you can remove the "import lxbuildenv" line) | 09:17 |
| tpb | Title: Sample CSR failing simulation · GitHub (at gist.github.com) | 09:17 |
| xobs | mithro: can you give an example of how CSR simulation is wrong if you don't make it a submodule? | 09:20 |
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| _florent_ | xobs: ok thanks | 09:21 |
| _florent_ | xobs: is the issue happening only when write_from_dev is set to True? | 09:22 |
| xobs | _florent_: I get a variety of errors. When I use a straight CSR, it gives the error "AttributeError: 'CSR' object has no attribute 'get_fragment_called'" | 09:25 |
| xobs | https://gist.github.com/xobs/77c6aaacc08fc2ad50e254b339c5e121 | 09:25 |
| tpb | Title: An example of CSRs failing with "AttributeError: CSR object has no attribute get_fragment_called" · GitHub (at gist.github.com) | 09:25 |
| xobs | It does work if I don't put it under "self.submodules". I wonder what issues mithro is seeing, then... | 09:30 |
| _florent_ | i think mithro wants to be able to simulate the write_from_dev behaviour, and that's why the self.submodules is used | 09:51 |
| xobs | _florent_: I don't see csr values getting updated at all. Should this test program work? https://gist.github.com/xobs/528c30d20a88268614bf7cdebc9f5a65 | 10:04 |
| tpb | Title: csr-test4.py · GitHub (at gist.github.com) | 10:04 |
| xobs | When I run that, test_value.r doesn't ever get updated. | 10:07 |
| _florent_ | xobs: in a SoC, the CSR are collected with the CSRBankArray Module and this one adds the CSR as submodules | 10:09 |
| _florent_ | xobs: i'm don't think we should add the CSR to submodules manually | 10:10 |
| mithro | xobs: I have a test somewhere... Did you find my bug | 10:11 |
| xobs | mithro: ah, it's a pull request: https://github.com/enjoy-digital/litex/pull/131 | 10:12 |
| tpb | Title: WIP: Add test for CSRs and fix in simulation. by mithro · Pull Request #131 · enjoy-digital/litex · GitHub (at github.com) | 10:12 |
| mithro | xobs: Look at that, past me even included an example / test | 10:13 |
| xobs | thanks, past mithro! | 10:13 |
| mithro | xobs: I think the question is why I needed two yields and why the csrs where being weird like this... | 10:14 |
| xobs | mithro: isn't it one cycle to get it into the buffer, and one to read it back out? that doesn't surprise me. | 10:15 |
| mithro | xobs: It doesn't work that way | 10:16 |
| mithro | xobs: Any time the clock toggles and we is 1, it should update the CSR | 10:16 |
| mithro | yield should equal one clock toggle... | 10:16 |
| xobs | So yield changes the clock twice? Once for negedge, and once for posedge? | 10:18 |
| mithro | xobs: As far as I understand | 10:19 |
| xobs | mithro: I wonder if that means we can't do DDR for spi flash. | 10:23 |
| mithro | For spiflash you shouldn't be using the system clock | 10:24 |
| xobs | Anyway, it's nice to know that you're supposed to use accessors for reading and writing csr values, and not accessing the values directly. | 10:24 |
| xobs | _florent_: mithro what's the status of that PR? Or rather, how should I reliably simulate CSRs? | 10:45 |
| mithro | xobs: I can't recall... | 10:46 |
| rohitksingh_work | mithro: Hi! :) Mike "hamster" was asking about "Do you know a Verilog guru who can point out all my stylistic flaws in my Veriog? I am sure it is not using the Verilog idioms and could be improved or made more concise. " Whom do you recommend I point him to? Clifford? OlofK? Whitequark? | 11:13 |
| mithro | rohitksingh_work: Clifford maybe? | 11:51 |
| mithro | rohitksingh_work: olofk is more of an ASIC person... | 11:51 |
| rohitksingh_work | mithro: ok, thanks! | 12:05 |
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| CarlFK | mithro: qemu-system-or1k ... build/arty_net_or1k//software/bios/bios.bin | 14:05 |
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| CarlFK | mithro: 39../sysdeps/unix/sysv/linux/ppoll.c: No such file or directory. | 14:05 |
| CarlFK | mithro: works on bionic, errors ^^ on cosmic | 14:05 |
| CarlFK | mithro: where should I report this? | 14:06 |
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| CarlFK | mithro: ignore ppoll.c: No such file | 14:50 |
| CarlFK | mithro: #qemu pm215: "Unhandled exception 6" is a problem within the guest -- the guest code has reported that it took an unexpected error | 14:50 |
| CarlFK | http://paste.ubuntu.com/p/k5KVYzZFQk/ H2U 00:00:00> *** Unhandled exception 6 *** | 14:50 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 14:50 |
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