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| synaption[m] | hey I have a migen question | 07:15 |
|---|---|---|
| synaption[m] | I was trying to figure out if migen would be usable with qFlow for VLSI design, but It looks like migen code gets boiled down to FHDL witch seems to be different than verilog. Is there a way to get verilog or VHDL from migen? | 07:19 |
| synaption[m] | nvm, I seem to have answered my own question | 07:42 |
| synaption[m] | Any FHDL module can be converted into synthesizable Verilog HDL. This is accomplished by using the convert function in the migen.fhdl.verilog module | 07:42 |
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