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| nats` | mithro, could you point me what I have to do to port timvideos to genesys2 in that case ? | 09:14 |
| nats` | because i'm not sure what's missing | 09:14 |
| mithro | nats`: create platform/genesys2.py then create targets/genesys2/.... | 09:16 |
| nats` | but why we don't take the one from litex ? | 09:16 |
| nats` | there is something I don't get | 09:16 |
| mithro | nats`: Probably start with base.py, then net.py, etc | 09:16 |
| mithro | nats`: https://github.com/timvideos/litex-buildenv/blob/master/platforms/atlys.py#L615-L634 | 09:17 |
| tpb | Title: litex-buildenv/atlys.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 09:17 |
| nats` | I took a look at that I used that to start the porting but you pointed that it already exists in an other repo | 09:18 |
| nats` | my point is why we don't get it from that repo ? | 09:18 |
| nats` | https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/genesys2.py | 09:35 |
| tpb | Title: litex/genesys2.py at master · enjoy-digital/litex · GitHub (at github.com) | 09:35 |
| nats` | I have almost the same and I need to finish the HPC | 09:36 |
| nats` | so exactly the same status | 09:36 |
| nats` | maybe i should finish what's already started more than reworking everything | 09:37 |
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| mithro | nats`: Sorry got distracted | 10:28 |
| mithro | nats`: The reason we don't reuse the one from litex is a bit historical | 10:28 |
| mithro | nats`: Maybe we need revisit how to do that | 10:29 |
| mithro | nats`: I know that cr1901_modern has opinions on that :-P | 10:29 |
| nats` | uhhmm ok I'll wait for result of that thinking :D | 10:50 |
| nats` | I don't want to be in the middle of a 'political' war :D | 10:51 |
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| mithro | nats`: It's more of nobody has had the time to clean it up, get our changes upstream and check that it doesn't break things | 10:56 |
| mithro | I think the biggest blocker is cleaning up the spi module stuff | 10:58 |
| mithro | # Micron N25Q128 (ID 0x0018ba20) | 10:59 |
| mithro | # FIXME: Create a "spi flash module" object in the same way we have SDRAM | 10:59 |
| mithro | # module objects. | 10:59 |
| _florent_ | mithro, nats: i need to keep some platforms in litex for regression testing and the projects i'm working on, but you are free to copy platforms and or targets from litex to litex-buildenv | 11:05 |
| mithro | nats`: So, no big deal to copy | 11:06 |
| nats` | cool ok | 11:12 |
| cr1901_modern | mithro, nats: Relevant issue is here: https://github.com/timvideos/litex-buildenv/issues/28 Fixing this issue has taken a backseat for me for various reasons. | 11:13 |
| tpb | Title: Reunite `litex-buildenv` with LiteX platforms · Issue #28 · timvideos/litex-buildenv · GitHub (at github.com) | 11:13 |
| mithro | https://twitter.com/field_hamster/status/1087252701744836608 woot! | 11:17 |
| nats` | I should do that with my HDMI2 core I guess | 11:19 |
| nats` | but it uses GTP from artix... | 11:19 |
| felix_ | why verilog and not (n)migen? /o\ | 11:21 |
| cr1901_modern | Learning a language == time commitment, he may want to limit the uncertainty of things going wrong on this project by using what he's used to | 11:24 |
| daveshah | VHDL -> Verilog is easier than VHDL -> Migen I suspect | 11:25 |
| daveshah | Certainly when doing my CSI-2 receiver it was quite mechanical to take it to Verilog | 11:25 |
| nats` | and at least verilog is really used everywhere and pretty generic | 11:26 |
| felix_ | yeah, migen is quite different to vhdl/verilog and it took me quite a while to get used to it. verilog is a horrible language though... | 11:26 |
| nats` | uhhmm I still can't opensource my HDMI2 core.... the documentation is still not public :| | 11:27 |
| nats` | there are shitty part in HDMI2 making things complicated to opensource without taking some risk | 11:27 |
| daveshah | It is leaked at least now | 11:29 |
| daveshah | https://glenwing.github.io/docs/HDMI-2.0.pdf | 11:29 |
| nats` | sure but I'm not sure it's a good idea | 11:30 |
| nats` | the hdmi forum can be really agressiv | 11:30 |
| nats` | I worked in a related field for few years and they are not the kind of "nice guy" | 11:30 |
| daveshah | Yeah | 11:30 |
| nats` | anyway the only big difference is in fact the scrambling system to activate once you go higher than 300MHz clock | 11:31 |
| daveshah | There's a reason the ULX3S FPGA boards are being sold with "GPDI" connectors | 11:31 |
| nats` | and the fact that you need to divide clock at those rate too | 11:31 |
| nats` | hehe nice rename :) | 11:31 |
| cr1901_modern | General Purpose Differential Interface? | 11:32 |
| daveshah | > GPDI is General Purpose Differential Interface, Electrically LVDS, mostly TMDS tolerant female receptacle more-or-less compatible with digital monitors/TVs | 11:32 |
| nats` | I'm wondering how this pdf was cleaning | 11:33 |
| nats` | the one I have is watermarked with the name of my former boss company | 11:33 |
| nats` | was cleaned | 11:33 |
| daveshah | Dewatermarking is quite common in this world... | 11:34 |
| cr1901_modern | Well for those who pirate photoshop anyway | 11:34 |
| nats` | oky I'm not aware of all those tricks :) | 11:35 |
| daveshah | https://glenwing.github.io/docs/ | 11:35 |
| tpb | Title: Display Industry Standards and Specifications (at glenwing.github.io) | 11:35 |
| daveshah | Grab em before they go | 11:36 |
| nats` | https://i.imgur.com/4Z8JgHd.jpg | 11:36 |
| cr1901_modern | I suggest wget's --mirror option :) | 11:36 |
| cr1901_modern | (No don't, that's actually rather inconsiderate) | 11:36 |
| nats` | https://i.imgur.com/OHM7xu2.jpg | 11:36 |
| nats` | those were my test :) | 11:37 |
| nats` | and I managed to do that on artix 7 with timing in the tens of picosecond range | 11:37 |
| daveshah | I did 4k30 DVI once from an old Xilinx devboard, with a 4k TV via HDMI adapter (effectively 1.4) | 11:37 |
| daveshah | This was using the parallel to DVI chip onboard | 11:37 |
| daveshah | Running said chip at about twice its rated maximum pixel clock | 11:38 |
| daveshah | Surprisingly, that ran rock solid but got a bit warm | 11:38 |
| nats` | not that surprising in fac t:) | 11:38 |
| nats` | DVI/HDMI are really tolerant | 11:38 |
| nats` | I managed to get a working signal with something like 5x less amplitude | 11:38 |
| daveshah | Yeah, I was most surprised that the PLL in that chip was able to lock at 2x its expected upper frequency | 11:39 |
| nats` | uhhmmm did you actually test that assumption :D | 11:40 |
| nats` | I ask because in fact on a lot of screen I managed to get a picture with clock at a lower rate :) | 11:41 |
| nats` | (still integer multiple) | 11:41 |
| daveshah | Yes it was definitely running at the proper rate | 11:41 |
| nats` | so 297MHz or something like that vs 148.5 ? | 11:42 |
| daveshah | Yeap | 11:42 |
| nats` | that's pretty impressive indeed :) | 11:42 |
| daveshah | Connected to a camera running at 4k30 too | 11:43 |
| nats` | in fpga the main problem is their weird running sum | 11:43 |
| nats` | it makes that point hard to pipeline because you have dependencies between pixel | 11:43 |
| nats` | and when you work with GTP you have to pack the pixel 4by 4 on each lane | 11:44 |
| daveshah | Yeah | 11:44 |
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