Thursday, 2018-12-27

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rohitksinghxobs, mithro: Hi! :) https://twitter.com/johndmcmaster/status/1078249569660604416 Happy hacking with tinyusb and fomu! I spot esden also in the corner11:38
mithrorohitksingh: Your at 35c3?11:53
mithrorohitksingh: Did you see I fixed the build for the Mimas A7?11:53
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rohitksinghmithro: oh, no...I just saw you and xobs in the JohnDMcmaster's tweet.13:08
rohitksinghmithro: Yup, I saw you rebuilt the Xilinx toolchain archive :)13:09
rohitksinghI'm currently trying to get video target on Mimas A7 to work13:09
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rohitksinghmithro/_florent_: can you point me how to remove/disable existing triggers in litescope?13:48
tumbleweed3714:08
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_florent_rohitksingh: i can help but i'm not sure to understand your question sorry15:25
CarlFKmithro: are you talking?  or really, which stream should I play for the next few days?15:32
xobsHe's speaking tomorrow.15:32
xobsClarke: https://fahrplan.events.ccc.de/congress/2018/Fahrplan/schedule/2.html15:32
tpbTitle: Schedule – 2018-12-28 | Schedule 35th Chaos Communication Congress (at fahrplan.events.ccc.de)15:32
CarlFKthanks15:33
CarlFKaccording to this, there is only one track: music.  https://fahrplan.events.ccc.de/congress/2018/Lineup/events.html15:33
tpbTitle: Events | Schedule 35C3 Art'n'Beauty Fahrplan (ABFahrplan) (at fahrplan.events.ccc.de)15:33
xobsThat's the "Art'n'Beauty Fahrplan"15:34
xobshttps://fahrplan.events.ccc.de/congress/2018/Fahrplan/events.html15:35
tpbTitle: Events | Schedule 35th Chaos Communication Congress (at fahrplan.events.ccc.de)15:35
CarlFKah I see what happened.  websites are hard.15:35
rohitksingh_florent_: sorry if I wasn't clear....I meant, if I add any trigger to litescope using add_rising_edge_trigger() function and then run the analyser, but if that trigger never fires, then is there any way to disable that trigger (or force capture/fire the analyser immediately)15:54
rohitksingh_florent_: also one similar doubt: sometimes the trigger fifo becomes full (most likely because I'm not using it correctly)...is there any way to reset/empty it?15:55
rohitksingh_florent_: does this capture look weird to you in any way? https://www.dropbox.com/s/ii6q555bt11pt8s/Screenshot_20181227_221240.png?dl=0 It is the litescope capture of hdmi out core's dma and timing generator modules...I can't figure out what's wrong with the litevideo...it is not giving any output (not even pattern)16:54
tpbTitle: Dropbox - Screenshot_20181227_221240.png (at www.dropbox.com)16:54
rohitksinghissue is with mimas_a7's video target. even nexys_video's video target seems broken due to regression16:55
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rohitksingh_florent_: okay, further info which may help figure the issue: the vsync frequency is 6Hz instead of expected 60Hz https://www.dropbox.com/s/ceutcxy0tlreqta/Screenshot_20181228_010121.png?dl=0 seems to be either issue with TimingGenerator module or MMCM/PLL clock configuration in gateware/firmware....any ideas?19:39
tpbTitle: Dropbox - Screenshot_20181228_010121.png (at www.dropbox.com)19:39
rohitksingh^ first trace is of vsync from "Driver" module, second is for vsync from "TimingGenerator" module, same frequency19:41
rohitksinghokay, got it....the pixel clock itself is 6.5MHz, thanks to the help from cr1901_modern's frequency counter20:10
rohitksinghmithro/_florent_: looks like the issue might be with the dynamic MMCM configuration in firmware...trying to pin-point the main problematic code...21:14
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futarisIRCcloudrohitksingh: We were fiddling around with the clocks on series 7 FPGAs around this time last year, to get VGA out working.22:38
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