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| tannewt | mithro, I do have ICE40UP5k and ICE408k dev boards too | 06:47 |
|---|---|---|
| tannewt | bxes are scheduled to come monday | 06:47 |
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| CarlFK | rohitksingh: hi! | 18:48 |
| tannewt | mithro, are you working usb today at all? | 18:48 |
| rohitksingh | CarlFK: hi! | 18:48 |
| mithro | tannewt: yeap! | 18:49 |
| mithro | tannewt: probably be starting in like an hour | 18:49 |
| mithro | I'll not a morning person :-P | 18:49 |
| tannewt | mithro: kk, I'll plan on being around. would be good to get me setup with litescope. | 18:50 |
| mithro | Have you got MicroPython booting on anything yet? | 18:54 |
| tannewt | no but I did install the environment | 18:55 |
| tannewt | I'll get the arty going | 18:55 |
| CarlFK | is that this? https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-a-Digilent-Arty-A7 | 18:56 |
| tpb | Title: HowTo FuPy on a Digilent Arty A7 · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 18:56 |
| tannewt | ya | 18:58 |
| mithro | tannewt: what were the other Dec boards you had? | 19:00 |
| tannewt | the 8k and the 5up | 19:01 |
| tannewt | from lattice | 19:02 |
| mithro | tannewt: might try https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards too | 19:04 |
| tpb | Title: HowTo FuPy on iCE40 Boards · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 19:04 |
| tannewt | k | 19:04 |
| CarlFK | in #pumpingstationone: bjonnh: I'm trying to get the largest dense matrix from my sparse matrix | 19:04 |
| CarlFK | he is working with "under 64gig of data" | 19:05 |
| CarlFK | what fpga board can host? 64g of ram? | 19:05 |
| daveshah | Plenty of FPGA boards can host 64GB of RAM | 19:06 |
| daveshah | The question is how many can make effective use of it | 19:06 |
| CarlFK | are you talking about the hardwired? interface, or the hacker's fpga skill ? | 19:08 |
| tannewt | mithro any schematics available for the new tomu? I can solder it up | 19:09 |
| daveshah | CarlFK: hacking something on eg to an FMC connector | 19:10 |
| daveshah | Don't know how many have actual support for something like that | 19:10 |
| daveshah | https://www.electronicspecifier.com/boards-and-backplanes/fpga-board-features-support-for-up-to-256gb-of-ddr4 | 19:11 |
| tpb | Title: FPGA board features support for up to 256GB of DDR4 (at www.electronicspecifier.com) | 19:11 |
| daveshah | hi tannewt btw | 19:11 |
| daveshah | You did the original ultraplus that I continued didn't you | 19:11 |
| tannewt | hi daveshah ! nice talk on the ecp5 at ORConf. I watched it last night! | 19:11 |
| tannewt | ya, I started it :-) | 19:12 |
| CarlFK | next q: what are the chances of micropython doing something like threads, even if it was a new vm chewing up gobs of ram? | 19:14 |
| daveshah | thanks tannewt! | 19:15 |
| CarlFK | bjonnh is doing R&D, he has a run down to 45min. in python/numpy. if his task could be parallelized, a 10x boost would be super beneficial. 100x would be super cool, but the edge of useful. | 19:20 |
| tannewt | how do I exit the litex env so I can change the platform? | 19:23 |
| tannewt | CarlFK: I think micropython can do basic threads | 19:24 |
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| CarlFK | tannewt: litex env - I think you set the vars and re-run source ./scripts/enter-env.sh | 19:26 |
| mithro | tannewt: you can just change the environment variables, no need to exit | 19:28 |
| tannewt | I sorted it out... and then kworker hung so I had to restart | 19:32 |
| tannewt | ok, back and hopefully won't hang | 19:58 |
| mithro | tannewt: What is your github username? | 20:02 |
| tannewt | mithro, tannewt as well | 20:20 |
| tannewt | (sorry I was soldering) | 20:20 |
| CarlFK | daveshah: any idea what it costs? this doesnt help: https://www.bittware.com/fpga/xusp3r/#pricinginfo | 20:25 |
| tpb | Title: XUSP3R - BittWare (at www.bittware.com) | 20:25 |
| daveshah | I would guess its classic a case of if you have to ask then you can't afford it | 20:27 |
| mithro | CarlFK: probably like $USD 20k | 20:28 |
| CarlFK | ok thats out. | 20:29 |
| mithro | CarlFK: you are unlikely to get a FPGA board with 256gb ram which isn't like 20k+ | 20:30 |
| CarlFK | mithro: how about a pcie card that can use a PC's 256g ram? | 20:34 |
| mithro | CarlFK: what are you trying to do? | 20:34 |
| CarlFK | mithro: in #pumpingstationone: bjonnh: I'm trying to get the largest dense matrix from my sparse matrix | 20:34 |
| CarlFK | mithro: his dataset is "under 64g" and he has runs down to 45 min | 20:35 |
| daveshah | I wouldn't be surprised if a better CPU implementation is the best way forward | 20:35 |
| mithro | /maybe/ a GPU solution | 20:35 |
| mithro | But I doubt an FPGA would help here | 20:36 |
| CarlFK | daveshah: for practical values of best ;) | 20:36 |
| CarlFK | he is already doing the work in python, so if the code could be run on both cpython and micropython, it would help verify the results | 20:37 |
| CarlFK | and advance micropython on fpga | 20:38 |
| daveshah | An optimised fpga solution certainly won't involve micropython! | 20:40 |
| daveshah | It sounds like using the optimised instruction set of modern CPUs might be a way forward, almost certainly an improvement over Python | 20:41 |
| CarlFK | daveshah: that's why I mentioned that we don't need 100x improvement | 20:41 |
| daveshah | You presumably also don't want a 100x slowdown | 20:41 |
| CarlFK | lol | 20:41 |
| CarlFK | we are at 45 min on cpython/numpy. lets assume 8 runs a day. if it takes 8 hours of work to get 10x, thats paid for itself in 2 days | 20:43 |
| mithro | CarlFK: Your not going to get 10x faster on an FPGA in just 8 hours of work | 20:43 |
| mithro | CarlFK: Maybe 80 hours if your very good | 20:44 |
| mithro | tinyfpga: Were you just exporting the verilog from tinyusb and importing into icecube2 manually? | 20:45 |
| CarlFK | mithro: the hope was micropython parallel threads would be faster than cpython cpu | 20:45 |
| mithro | CarlFK: Not a chance | 20:45 |
| mithro | CarlFK: Doesn't work that way at all | 20:48 |
| CarlFK | mithro: ok, what about using python to populate memory, and porting the needed numpy algorithms to risk/C, and parallelizing that? (yes, slinging words around loosely) | 20:50 |
| CarlFK | part of the plan is being able to use the cpu cpython/numpy code to verify the results on the runs that seem interesting | 20:51 |
| tannewt | I thought numpy was mostly implemented in C anyway | 20:53 |
| CarlFK | tannewt: im guessing it will take a bit to make it work on micropyton/soft core (risk 5?) | 20:55 |
| tannewt | yes, definitely | 20:56 |
| tannewt | numpy is not small | 20:56 |
| tannewt | most cpython libs contain the kitchen sink | 20:56 |
| daveshah | You would also be looking at a very special soft core | 20:57 |
| CarlFK | more hope was that only the parts needed for this project can be "ported" (is that the right word?) | 20:57 |
| mithro | tannewt: The risc-v core is substantially slower than your computer's CPU | 20:57 |
| mithro | Opps | 21:03 |
| mithro | CarlFK: The risc-v core is substantially slower than your computer's CPU | 21:03 |
| CarlFK | mithro: the cpu has a few cores. how does that translate to risk-v core? like is there a config option cores=100 ? | 21:06 |
| mithro | CarlFK: nope, we only really support a single core at the moment | 21:07 |
| CarlFK | mithro: rats. ok, thats the end of that. | 21:07 |
| mithro | Even if we did, I doubt it would be better than a GPU | 21:08 |
| daveshah | Or something like a Xeon Phi | 21:08 |
| mithro | CarlFK: the SoftCPU in our FPGA is a low performance "management" engine | 21:10 |
| mithro | It's there to do non-performance critical stuff to manage the specific function stuff | 21:11 |
| mithro | daveshah: how do I use the multiple clock domain stuff in nextpnr? | 21:12 |
| daveshah | mithro: https://github.com/YosysHQ/nextpnr/blob/master/docs/constraints.md#clock-constraints | 21:12 |
| tpb | Title: nextpnr/constraints.md at master · YosysHQ/nextpnr · GitHub (at github.com) | 21:12 |
| daveshah | If you just want reports, it will print them for all clocks by default | 21:12 |
| daveshah | I wouldn't expect constraints to make that much difference as it stands | 21:13 |
| CarlFK | k - I was hoping that investing a day or so porting generic things would help the micropython worls and give bjonnh a 10x boost | 21:13 |
| CarlFK | help the micropython world | 21:14 |
| mithro | daveshah: well, the USB clock needs to be greater than 48mhz | 21:14 |
| tannewt | mithro: are you developing on the tomu or the bx? I'm wondering if its worth soldering wires to the tiny pads | 21:32 |
| mithro | tinyfpga-bx for the moment | 21:32 |
| mithro | Until I get things going | 21:32 |
| tannewt | makes sense | 21:32 |
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| mithro | cr1901_modern: ping? | 22:33 |
| tannewt | is there a specific baudrate needed for the serial to a up5k evn board? | 22:33 |
| tannewt | I think micropython loaded ok but don't get any serial | 22:34 |
| daveshah | I thought the EVN doesn't have serial | 22:34 |
| daveshah | You might need to add pins | 22:34 |
| mithro | daveshah: https://github.com/timvideos/litex-buildenv/wiki/HowTo-FuPy-on-iCE40-Boards#ice40-ultraplus-breakout-board | 22:34 |
| tpb | Title: HowTo FuPy on iCE40 Boards · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 22:34 |
| tannewt | ya, I soldered to the ones in the platform file and hooked up a usb to serial converter | 22:34 |
| daveshah | mithro: yup, don't know why Lattice were that stupid | 22:35 |
| tannewt | https://github.com/timvideos/litex-buildenv/blob/master/platforms/ice40_up5k_b_evn.py | 22:35 |
| tpb | Title: litex-buildenv/ice40_up5k_b_evn.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 22:35 |
| daveshah | I'm sure the hx8k breakout has serial | 22:35 |
| tannewt | it says 48b and 51a | 22:36 |
| mithro | https://github.com/timvideos/litex-buildenv/blob/master/targets/ice40_up5k_b_evn/base.py | 22:36 |
| tpb | Title: litex-buildenv/base.py at master · timvideos/litex-buildenv · GitHub (at github.com) | 22:36 |
| * mithro goes to delete that obsolete information... | 22:37 | |
| tannewt | https://usercontent.irccloud-cdn.com/file/OsvW3bmo/IMG_2979.JPG | 22:38 |
| tannewt | taking a break now to play some fallout. my linux box is still soft hanging pretty frequently | 22:39 |
| mithro | tannewt: Do you know how to filter wireshark usb capture to just anything below a given hub? | 22:51 |
| tannewt | no, I usually use a beagle which does just the one device | 23:11 |
| mithro | _florent_: You happen to be around? | 23:14 |
| mithro | Just wondering how you use LiteScopeIO | 23:15 |
| mithro | In [5]: wb.regs.io_out.write(0x1) | 23:19 |
| mithro | In [6]: wb.regs.io_out.write(0x0) | 23:19 |
| mithro | Just like that it seems.. | 23:19 |
| mithro | This looks promising... | 23:20 |
| mithro | [414884.260173] usb 2-14.1: Device not responding to setup address. | 23:20 |
| mithro | [414884.472182] usb 2-14.1: Device not responding to setup address. | 23:20 |
| tannewt | are you acking the setup packet? | 23:21 |
| mithro | tannewt: probably not | 23:23 |
| mithro | tannewt: But the fact that something is happening at all is potentially good :-P | 23:23 |
| tannewt | yup! you've taken the pins out of reset :-) | 23:24 |
| mithro | tannewt: I can toggle it in and out of reset by using the io_out module... | 23:25 |
| mithro | No I just have to remember how to litescope to capture the data.... | 23:25 |
| mithro | daveshah: Did nextpnr start consuming a lot more memory when compiling the database for the ice40? | 23:34 |
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