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| mithro | tannewt: Hi! | 00:22 |
|---|---|---|
| tannewt | hi hi @mithro | 00:22 |
| tannewt | I'm wrapping up a meeting atm | 00:22 |
| mithro | No worries | 00:22 |
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| tannewt | @mithro ready when you are | 00:31 |
| mithro | Okay - won't be a moment | 00:31 |
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| tannewt | ok, trying irccloud now | 02:48 |
| CarlFK | tannewt: http://matrix.org/ https://github.com/vector-im/riot-android/ scroll down, "get it on goog play" | 02:52 |
| tpb | Title: Home | Matrix.org (at matrix.org) | 02:52 |
| CarlFK | python -m SimpleHTTPServer 8007 | 03:49 |
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| xobs | Does anyone happen to have any documentation on the ICE40 NVCM blocks? Like (1) how do you program them, and (2) how does that state machine work? I know it's OTP, but can you read the contents back? | 10:13 |
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| xobs | Oh, apparently it's designed so you can't read it back. | 10:20 |
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| xobs | And I see a discussion mithro had ages ago about that very thing. | 12:10 |
| daveshah | You can have a look at the SVF files that Diamond programmer can generater | 12:11 |
| daveshah | My vague understanding is that you send an unlock command then treat it similar to a SPI flash | 12:11 |
| daveshah | but I haven't ever looked in great detail | 12:11 |
| xobs | <xobs "And I see a discussion mithro ha"> Thanks, daveshah, that seems the easiest way to do it. | 12:13 |
| daveshah | If you had an iCE40 to sacrifice, looking at the SPI commands with an LA over the wire would be reasonable too | 12:14 |
| daveshah | I thought I saw that there is some kind of verify command | 12:14 |
| daveshah | maybe it is read-locked by a config bit rather than automatically | 12:14 |
| xobs | I'll have a few soon. | 12:15 |
| mithro | xobs: its programmed very much like programming spi - there is a document with diagrams and everythink | 12:16 |
| xobs | mithro: I see. I haven't found that document yet, just one that says to "contact Lattice" | 12:16 |
| mithro | https://usercontent.irccloud-cdn.com/file/1UQRspvy/Screenshot%20from%202018-11-15%2004-10-03.png | 12:16 |
| daveshah | I'm pretty sure the secret unlock command isn't published | 12:17 |
| daveshah | not that it's hard to discover either | 12:17 |
| xobs | Fancy! Congratulations on the new boards. | 12:17 |
| daveshah | Looks awesome!! | 12:17 |
| mithro | what am I missing, why does the solder mask cover any of that middle region? | 12:19 |
| mithro | shouldn't I be seeing bare FR4 with traces? | 12:19 |
| mithro | https://www.latticesemi.com/-/media/LatticeSemi/Documents/WhitePapers/NZ/SecurityAspectOfLatticeSemiconductor-English-090313.ashx?document_id=50737 | 12:21 |
| daveshah | mithro: maybe the pcb fab "fixed" it for you | 12:25 |
| mithro | well, that is what I'm wondering | 12:26 |
| daveshah | they do have a tendency to mess with the soldermask layer | 12:26 |
| mithro | I actually think they may have used the paste layer? | 12:26 |
| xobs | Yeah, ask for the check plots. | 12:26 |
| mithro | https://usercontent.irccloud-cdn.com/file/LDyAfGTC/Screenshot%20from%202018-11-15%2004-20-41.png | 12:27 |
| mithro | xobs / daveshah: but I'm right in expecting the middle to not have any soldermask? | 12:27 |
| daveshah | based on the gerbers, yes | 12:28 |
| xobs | They sometimes (read: often) change what you send them. The check plots are what they actually make, so they should give them to you. | 12:32 |
| mithro | well, back to sleep for me | 12:49 |
| cr1901_modern | mithro: Did you make that yourself? | 12:50 |
| felix_ | mithro: i wonder why the pads in the outer ring of pads for the fpga aren't round, but instead long like the pads for a qfn chip | 13:12 |
| daveshah | I'm guessing this is a trick to be able to route traces between them | 13:12 |
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| mithro | cr1901_modern: Do you have any more information on the spi flash sleep mode thingy? | 16:49 |
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| cr1901_modern | mithro: ICE40 will by default tell the SPI flash to power down after it loads the bitstream. | 17:02 |
| cr1901_modern | There is a config bit (shared w/ warmboot/coldboot) that tells the FPGA to _not_ send the power down command | 17:02 |
| cr1901_modern | this is basically required if doing XIP because the FPGA softcore will immediately try running insns from SPI flash. If powered down, the CPU will read garbage | 17:09 |
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| mithro | cr1901_modern: So flashing is very unhappy when you are building a gateware without a bios | 21:50 |
| cr1901_modern | mithro: Which board? | 21:52 |
| mithro | cr1901_modern: tinyfpga_bx | 21:52 |
| cr1901_modern | That's excpected. The BIOS isn't embedded into the bitstream | 21:52 |
| cr1901_modern | you must flash the gateware and the BIOS | 21:52 |
| cr1901_modern | you can't just flash the gateware | 21:53 |
| mithro | cr1901_modern: This gateware doesn't have a bios, it just has the UART bridge | 21:53 |
| cr1901_modern | I don't know then | 21:53 |
| ZipCPU | If you are working with the TinyFPGA BX, you'll want to use the tinyfpga tools to load your design | 21:54 |
| ZipCPU | they get around the BIOS issue by loading the design at a separate starting address | 21:54 |
| ZipCPU | Once loaded, the design then runs | 21:54 |
| ZipCPU | But ... you can't load it at the zero address or you'll brick your board | 21:54 |
| cr1901_modern | I know for a fact the UART bridge has worked previously. | 21:55 |
| mithro | The bridge works fine if I make a zero size bios file | 21:57 |
| mithro | cr1901_modern: The issue is that you are forcing the gateware to flash a bios, and this design doesn't have a bios... | 21:57 |
| cr1901_modern | I guess one of the makefile rules needs to be changed then | 21:58 |
| ZipCPU | What do you mean by BIOS? Object code for a CPU? Or the bitstream loader that's unique to the TinyFPGA BX? | 21:58 |
| mithro | ZipCPU: Most LiteX SoC's have an embedded soft-cpu which initially boots to a bios that then loads the user firmware | 22:01 |
| ZipCPU | If that's what you mean by BIOS, then okay, that makes more sense. | 22:03 |
| mithro | https://www.irccloud.com/pastebin/blf4zYit/ | 22:08 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 22:08 |
| mithro | https://www.irccloud.com/pastebin/EZ9UhWyy/ | 22:11 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 22:11 |
| cr1901_modern | mithro: What is the exact error message you're seeing when trying to write out the bridge bitstream? | 22:15 |
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| CarlFK | mithro: where is the opsis power page you fixed? really I want the usb header pinout | 22:19 |
| mithro | Opsis.hdmi2usb.tv | 22:20 |
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| * CarlFK[m] uploaded an image: VectorImage_2018-11-15_044817.jpg (4666KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/fjUWPvPJxZmxXPGtnAttpewL > | 22:54 | |
| * CarlFK[m] uploaded an image: VectorImage_2018-11-15_044902.jpg (98KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/fWuArwNEPbOPbDywILeTSUji > | 22:55 | |
| CarlFK | opsis usb to usb-a connector in C2 - fits perfectly | 22:56 |
| CarlFK | no idea if it works | 22:56 |
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| mithro | CarlFK: Your colorscheme could use a lot of improvement... | 23:24 |
| CarlFK | mithro: i used the wires I was handed to me - this is prototype | 23:26 |
| CarlFK | also, I guessed at which way to hook it up and got it backwards. | 23:26 |
| mithro | CarlFK: Opps.... | 23:26 |
| CarlFK | good news: nothing fried. hooked up right, I got a console and all is well | 23:26 |
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| CarlFK | mithro: off to meet with Chris about KiCad conf - see ya | 23:31 |
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