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| cr1901_modern | mithro: https://logs.timvideos.us/%23timvideos/%23timvideos.2018-09-08.log.html#t2018-09-08T06:15:25 | 00:11 |
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| cr1901_modern | I'm going to deliberately increase the SRAM size to force a compile, but why don't we see which beefy symbols/variables can be trimmed out if we are tight on SRAM (using a new preprocessor define as well)? | 00:12 |
| mithro | cr1901_modern: just use a smaller firmware to start with? | 00:13 |
| cr1901_modern | I suppose that works too as long as you don't have a problem with something like a "stub" firmware directory (analogous to what _florent_ has for tinyfpga-soc) | 00:16 |
| cr1901_modern | mithro: ^^ | 00:26 |
| mithro | Sure | 00:29 |
| mithro | Lets get it in ASAP | 00:29 |
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| fitzsim | mithro: no, I've never built any RISC-V toolchain stuff before | 01:57 |
| fitzsim | mithro: for your purposes, I would just copy that recipe, and remove everything | 01:57 |
| fitzsim | mithro: then change all the relevant fields to point to an HX8K example bitfile | 01:58 |
| fitzsim | mithro: its "make" target should work, and generate a bit file in a recipe | 01:58 |
| fitzsim | mithro: since you're already at the point where you have all the iCE40 tools built, and staged in the sysroots | 01:58 |
| shorne | mithro: I was asking about qemu devicetree on #qemu no response yet. I looked more at the code, it seems there is not much 'configuration' done with device tree | 03:13 |
| shorne | the support in qemu is mostly for passing information to the kernel | 03:13 |
| shorne | ie. qemu generates device tree details and passes that down to the kernel | 03:14 |
| shorne | Myabe we can do that? i.e. pass device tree details to kernel or litex bios? when running in qemu | 03:15 |
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| * cr1901_modern shudders at the idea of litex-bios becoming device-tree aware | 03:23 | |
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| cr1901_modern | (nothing against you/you work shorne) | 03:23 |
| cr1901_modern | Just device-tree + cr1901 = Match made in hell (though I understand why it exists) | 03:23 |
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| cr1901_modern | mithro (If you're still awake): My sleep schedule is inverted (I've been working mostly at night the past few days). Chances are I'll make a PR for tinyfpga in litex-buildenv while you're asleep tonight. | 06:01 |
| cr1901_modern | mithro: Btw, perhaps we should consider moving some of the litex-buildenv firmare into its own support library that applications (such as stub firmware) can pick and choose to use. Just throwing darts and seeing what'll stick tho :P | 06:02 |
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| CarlFK | mithro: I finely got around to "git fetch upstream; git rebase -i upstream/master; git push origin mybranch --force" | 06:59 |
| xobs | I seem to remember that one trick to quicker peripheral debugging is to remove the CPU. However, I've changed BaseSoC.init() to specify cpu_type=None, and EtherboneSoC claims that "object has no attribute 'cpu_or_bridge'". How do I have BaseSoC create a bridge? | 07:08 |
| cr1901_modern | xobs BaseSoC.add_cpu_or_bridge | 07:47 |
| cr1901_modern | this could be documented better (<jest>PRs welcome</jest>) | 07:48 |
| xobs | cr1901_modern: Should I add the Etherbone bridge? Or, why isn't a bridge added when BaseSoC.__init__() is called? | 07:49 |
| cr1901_modern | xobs: TLDR; Yes to the first part, probably b/c you can add any WB peripheral you like to the bus as why __init__ doesn't create it. | 07:52 |
| cr1901_modern | While clearly, this level of internal impl shouldn't be necessary... The Etherbone bridge should have a "bus" attribute, and anything with the wishbone "bus" attribute can be passed on | 07:52 |
| xobs | Thanks, I'll try self.add_cpu_or_bridge(self.etherbone.bridge) and see if that builds. | 07:55 |
| xobs | LiteEthEtherbone has no attribute 'bis' or 'bridge' | 07:57 |
| xobs | 'bus' or 'bridge', my fault. | 07:57 |
| cr1901_modern | Try UARTWishboneBridge | 07:58 |
| xobs | That makes it happy. Why do I need to add a UARTWishboneBridge to it in order to get Ethernet working? Does Ethernet go over UART? | 07:59 |
| cr1901_modern | You don't | 07:59 |
| cr1901_modern | that makes the UART work :) | 07:59 |
| cr1901_modern | I just wanted to see if it still worked | 07:59 |
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| cr1901_modern | I've never used LiteEthEtherbone | 07:59 |
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| xobs | I'll probably need to rename the repo at some point, but I've cleaned up the wishbone stuff and refined litex-devmem2: https://github.com/xobs/wishbone-adapter | 09:43 |
| tpb | Title: GitHub - xobs/wishbone-adapter: An adapter for the Wishbone network, and in particular the Ethernet interface (at github.com) | 09:43 |
| xobs | It now supports using litex_server and communicating directly over Ethernet with "--target [addr] --direct" | 09:43 |
| xobs | In litex, how do I designate a signal as "inout"? I'm still working on the GPIO stuff. At least now I know Wishbone is getting memory mapped properly (Though I'm not sure why I need the UART). | 10:06 |
| xobs | In top.v, the pads are showing up as "input". How do I designate something as "inout", like the mdio or dq pads? | 10:06 |
| xobs | Ah, okay, I need to add another parameter to the Tristate module. Let's see if this synthesizes. | 10:09 |
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| xobs | It does, but it doesn't work. It seems like the "io_" prefix for an Instance enables "inout". Let's see if I can drop down an "IOBUF". | 10:32 |
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| cr1901_modern | xobs: I'm sure the Ethernet stuff works, I just don't know how to use it | 12:11 |
| cr1901_modern | and re: the io_ i_ p_ o_ stuff... oops, sorry I wasn't paying attention to answer your q :P | 12:12 |
| cr1901_modern | For once I'm trying to correct my poor sleeping habits | 12:12 |
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| xobs | Sleep is very good. | 12:57 |
| cr1901_modern | I should consider learning how to powernap | 13:02 |
| xobs | Or travel to the correct time zone. | 13:06 |
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| cr1901_modern | If only we weren't required by physical limitations to lose 1/3 of our lives | 13:24 |
| cr1901_modern | to involuntarily doing nothing | 13:25 |
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| mithro | cr1901_modern: Morning? | 17:08 |
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| CarlFK | mithro: can you review my PR soon so I can see how smooth the LCA howto is | 17:53 |
| CarlFK | shorne: is your qemu/litex ready for public consumption? (which is about 2 people total) | 17:56 |
| mithro | CarlFK: How do you keep screwing up indenting? | 17:56 |
| CarlFK | mithro: tabs. | 17:56 |
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| CarlFK | mithro: I tried to find a shell script linter that would warn me before I commited messed up scripts. best I could find was https://github.com/koalaman/shellcheck and it didnt' compain about mixed tabs and intending problems | 18:40 |
| tpb | Title: GitHub - koalaman/shellcheck: ShellCheck, a static analysis tool for shell scripts (at github.com) | 18:40 |
| mithro | CarlFK: Do you actually look at the pull request before you send it? | 18:51 |
| CarlFK | mithro: the file looks ok in vim, and I do a git diff which also doesn't show a problem | 18:53 |
| CarlFK | really it is ok as long as your vim settings are right, it is github's version that looks funny :p | 18:54 |
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| mithro | cr1901_modern: Soooo... pull request? | 23:58 |
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