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| CarlFK | what tool is used for schematic design? | 00:45 |
|---|---|---|
| CarlFK | kicad. never mind. | 00:46 |
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| mithro | cr1901_modern: https://github.com/m-labs/VexRiscv-verilog/issues/2 | 01:29 |
| tpb | Title: Add VexRISCV configuration suitable for iCE40 sized devices · Issue #2 · m-labs/VexRiscv-verilog · GitHub (at github.com) | 01:29 |
| cr1901_modern | mithro: I generated such a config, I'm trying to test it now... (like literally now) | 01:29 |
| cr1901_modern | I'll be up for a few hours still, since sleep is elusive during normal sleep hours it seems | 01:30 |
| mithro | cr1901_modern: We are about to start hacking on FuPy | 01:30 |
| mithro | cr1901_modern: Can you comment on that issue | 01:30 |
| cr1901_modern | mithro: done | 01:33 |
| mithro | cr1901_modern: Thanks! | 01:34 |
| cr1901_modern | I _really_ wish I saw the blurb about the d-cache bus earlier though | 01:34 |
| cr1901_modern | It's a waste of resources on ice40 to have a d-cache | 01:35 |
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| mithro | ewen: https://docs.google.com/document/d/1fA4Nt_UyEe1spX2gJT4Ld802-seeGAxNY0DdlPFcbN8/edit# | 01:47 |
| tpb | Title: FuPy on iCE40 - Google Docs (at docs.google.com) | 01:47 |
| mithro | ewen: and https://github.com/m-labs/VexRiscv-verilog/issues/2#issuecomment-415245819 | 01:48 |
| tpb | Title: Add VexRISCV configuration suitable for iCE40 sized devices · Issue #2 · m-labs/VexRiscv-verilog · GitHub (at github.com) | 01:48 |
| mithro | cr1901_modern: You were having issues with the lm32 on the ice40, right? | 01:51 |
| cr1901_modern | mithro: Yes. I'm taking an old repo for that and adding a vexriscv branch | 01:56 |
| synaption[m] | hi | 02:13 |
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| CarlFK | mithro: whats the fupy url? | 02:44 |
| mithro | fupy.github.io | 02:45 |
| cr1901_modern | Why does my tinyfpga soc keep rese- oh, the pin dedicated to reset is floating | 02:46 |
| cr1901_modern | that would be a good reason | 02:46 |
| * CarlFK[m] uploaded an image: VectorImage_2018-08-22_094415.jpg (332KB) < https://matrix.org/_matrix/media/v1/download/matrix.org/IbCTcGGWObAMUXLwPQhbxoUQ > | 02:49 | |
| CarlFK | fpga-ing here too | 02:49 |
| CarlFK | sorta :p | 02:50 |
| cr1901_modern | _florent_: Could you take a look at my two PRs to litex when convenient? They are quality-of-life changes, but really helpful | 03:14 |
| mithro | cr1901_modern: Merged | 03:22 |
| cr1901_modern | mithro: Thanks :P. Didn't know you have commit access to litex now | 03:24 |
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| mithro | https://github.com/fupy | 03:55 |
| tpb | Title: FPGA MicroPython (FuPy) · GitHub (at github.com) | 03:55 |
| cr1901_modern | I'm guessing not, but is Dolu1990 ever on IRC? | 03:58 |
| * cr1901_modern doesn't actually know scala, big shock | 03:58 | |
| mithro | ewen: It should be here -> https://github.com/timvideos/litex-buildenv/wiki/SoftCPUs | 04:09 |
| tpb | Title: Home · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 04:09 |
| mithro | ewen: But it is not :-P | 04:09 |
| mithro | ewen: I think "export CPU=vexriscv" ? | 04:09 |
| mithro | cr1901_modern: Could you help ewen get started with vexriscv on an arty? | 04:10 |
| mithro | ewen: Maybe CPU=picorv32 ? | 04:10 |
| cr1901_modern | ewen: "export BOARD=arty TARGET=base CPU=picorv32 HDMI2USB_ENV=1" should be enough to set your environment, then run "make" | 04:12 |
| mithro | ewen: https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain | 04:15 |
| mithro | ewen: Maybe? | 04:15 |
| mithro | ewen: Or https://github.com/SpinalHDL/VexRiscv#build-the-risc-v-gcc | 04:15 |
| tpb | Title: GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation (at github.com) | 04:15 |
| cr1901_modern | mithro: I would use the insns posted by clifford on picorv32 repo | 04:16 |
| cr1901_modern | I've compiled it successfully on Windows w/ minor tweaks to Makefile.in (texinfo BS causes building docs to fail, and makeinfo can't be disabled during a gcc build) | 04:17 |
| cr1901_modern | mithro: Sleep is about to take hold. I'm out tomorrow, but I should be here during the night | 04:35 |
| mithro | cr1901_modern: Okay | 04:41 |
| mithro | ewen: https://github.com/timvideos/litex-buildenv/pull/34/files | 04:43 |
| tpb | Title: WIP: Adding tinyfpga and RISC-V support by mithro · Pull Request #34 · timvideos/litex-buildenv · GitHub (at github.com) | 04:43 |
| tinyfpga | Ohh! | 04:45 |
| tinyfpga | mithro: anything for me to try out there? | 04:45 |
| mithro | tinyfpga: Not yet | 04:45 |
| mithro | CarlFK: Did you end up solving that lm32 LC error assertion thingy? | 04:49 |
| mithro | CarlFK: We finally ran into that here! | 04:49 |
| CarlFK | mithro: nope Aeva said "it looks like gcc has a different libs path" | 04:50 |
| CarlFK | mithro: but.. older OSs (like stuff from last year) don't have the problem | 04:51 |
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| mithro | export LANG=/usr/lib/locale/C.UTF-8/ | 05:23 |
| mithro | https://unix.stackexchange.com/questions/444102/loadlocale-c-nl-intern-locale-data-assertion-error | 05:23 |
| tpb | Title: debian - loadlocale.c _nl_intern_locale_data assertion error - Unix & Linux Stack Exchange (at unix.stackexchange.com) | 05:23 |
| mithro | CarlFK: That should gix the problem? | 05:23 |
| mithro | I think the LANG should be something like $CONDA_DIR/share/locale or something... | 05:32 |
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| ewen | mithro: https://github.com/timvideos/litex-buildenv/wiki/SoftCPUs now exists, with some vague information on supported soft CPUs | 05:52 |
| tpb | Title: SoftCPUs · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 05:52 |
| mithro | ewen: So I was thinking we should move towards using crosstool-ng for building the crosscompilers as that is what conda uses internally -> https://github.com/mithro/conda-hdmi2usb-packages/tree/crosstool-ng | 05:57 |
| tpb | Title: GitHub - mithro/conda-hdmi2usb-packages at crosstool-ng (at github.com) | 05:57 |
| mithro | nickzoic: https://github.com/timvideos/litex-buildenv/blob/master/doc/notes.md | 06:16 |
| tpb | Title: litex-buildenv/notes.md at master · timvideos/litex-buildenv · GitHub (at github.com) | 06:16 |
| mithro | ewen: https://github.com/mithro/lxbe-tool | 06:16 |
| tpb | Title: GitHub - mithro/lxbe-tool: LiteX Build Environment tool. (at github.com) | 06:16 |
| CarlFK | mithro: yay! | 06:19 |
| CarlFK | mithro: oh, missed the ? .. did it fix it? | 06:20 |
| CarlFK | going shopping bye - good luck! | 06:22 |
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| mithro | xobs: You had vexrisc-v debugging via network working at some point right? | 06:55 |
| xobs | mithro: That's the only method I've gotten working. Eventually I'll need to add JTAG debugging for other reasons. | 06:56 |
| xobs | https://github.com/timvideos/litex-buildenv/wiki/Debugging | 06:56 |
| tpb | Title: Debugging · timvideos/litex-buildenv Wiki · GitHub (at github.com) | 06:56 |
| mithro | xobs: At some point I'd like to try the JTAG debugging via something using MuraxSoC style? | 06:56 |
| xobs | That seems more like how the vexriscv people intended it to work. As opposed to gluing it to Wishbone like I did. | 06:58 |
| mithro | xobs: Did you have any more thoughts on my lxbe-tool stuff? | 06:58 |
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| mithro | xobs: It is likely I'll be doing recruiting for developing that over the next couple of days | 07:12 |
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| mithro | ewen: | 07:19 |
| mithro | https://www.irccloud.com/pastebin/lQ8dRAIB/ | 07:19 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 07:19 |
| mithro | SoC BIOS / CPU: VexRiscv / 100MHz | 07:19 |
| mithro | :-P | 07:19 |
| mithro | \o/ | 07:19 |
| ewen | mithro: Yay! So CPU=vexriscv and CPU=picorv32 seem to work to build BIOS. Currently CPU=picorv32 seems to be more challenging to build micropython... | 07:24 |
| xobs | mithro: The fundamental problem you're trying to solve is "How much do I trust the end-user's environment?" and answers range from "Not at all" (which results in a VM or Docker solution) to "Quite a bit" (which is what lxbuildenv.py does). Conda is somewhere in the middle, tending towards "Not at all". | 07:26 |
| ewen | mithro: The crt0 assembly that I can't build, due to missing include, is copied out of litex: third_party/litex/litex/soc/software/libbase/crt0-picorv32.S | 07:29 |
| mithro | xobs: Yes - the idea with the tool was to have "providers" which means that we can share all the common parts while still having different ideas on how much we trust stuff | 07:29 |
| xobs | mithro: I do like that notion. | 07:30 |
| ewen | mithro: the vexriscv (crt0-vexriscv.S) one is *much* simpler, with no includes | 07:30 |
| ewen | I'll try building with CPU=vexriscv instead | 07:30 |
| mithro | xobs: Like we all have to deal with the issues around bloody submodules | 07:30 |
| mithro | xobs: And installing python modules into the environment | 07:30 |
| mithro | xobs: And checking the versions of things.... | 07:31 |
| mithro | xobs: etc | 07:32 |
| mithro | xobs: Setting things like PYTHONHASHSEED and similar too :-P | 07:32 |
| xobs | Distro development is hard. | 07:32 |
| mithro | xobs: Yeah | 07:34 |
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| mithro | ewen -- FYI: https://github.com/enjoy-digital/tinyfpga-soc - This uses the minimal variant of LM32 that is now integrated in LiteX. - I tested it on B2, but someone else tested it on BX successfully. | 07:47 |
| tpb | Title: GitHub - enjoy-digital/tinyfpga-soc: TinyFPGA SoC based on LiteX (at github.com) | 07:47 |
| xobs | mithro: Oh, you were talking earlier about dcache/icache for vexriscv. What brought that on, and what did you end up doing? | 07:48 |
| xobs | I noticed Wishbone is hooked up through those caches. Is it possible to hook it up a different way? | 07:48 |
| mithro | xobs: Looks like it was fixed here -> https://github.com/enjoy-digital/litex/issues/85 | 07:49 |
| tpb | Title: Possible problem with DCACHE when using VexRiscv · Issue #85 · enjoy-digital/litex · GitHub (at github.com) | 07:49 |
| mithro | FYI - Hi _florent_! | 07:50 |
| _florent_ | Hi! | 07:53 |
| mithro | _florent_: We will be hacking on FuPy for the next ~5-6 days | 07:53 |
| _florent_ | cool, what are your goals for these 5-6 days? | 07:54 |
| xobs | mithro: I see, that addresses a cache bug that vexriscv had. When I briefly tried it I was having trouble building a vexriscv core with a smaller cache. Is it possible to have a 0-byte cache? Or, rather, what's the smallest cache that's possible while still having Wishbone support? | 07:58 |
| mithro | xobs: oh, that is a different issue | 08:05 |
| mithro | _florent_: get tinyfpga support into LiteX-BuildEnv and get micropython stuff upstream | 08:06 |
| mithro | xobs: https://github.com/m-labs/VexRiscv-verilog/issues/2 | 08:07 |
| tpb | Title: Add VexRISCV configuration suitable for iCE40 sized devices · Issue #2 · m-labs/VexRiscv-verilog · GitHub (at github.com) | 08:07 |
| mithro | xobs: Talks about no cache configurations there | 08:08 |
| mithro | ewen: https://github.com/fupy/micropython/pull/15 | 08:09 |
| tpb | Title: Include files from litex. by mithro · Pull Request #15 · fupy/micropython · GitHub (at github.com) | 08:09 |
| mithro | _florent_: We have Nick Zoic who is a MicroPython maintainer here... | 08:11 |
| mithro | and will probably talk to other micropython people tomorrow... | 08:11 |
| _florent_ | mithro: ok interesting! | 08:12 |
| _florent_ | for tinyfpga support into LiteX-BuildEnv, you will probably need to run the firmware directly (without the bios), or run code from the flash | 08:14 |
| mithro | _florent_: Yeah - similar to how the MimasV2 works | 08:27 |
| _florent_ | ok good, i wasn't aware you were already doing that on MimasV2 | 08:28 |
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| futarisIRCcloud | mithro: Is everyone that is working on micropython for tinyfpga in Sydney for PyCon AU 2018? | 09:08 |
| futarisIRCcloud | And which tinyfpga(s) are you targeting? | 09:09 |
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| mithro | futarisIRCcloud: yes | 09:41 |
| mithro | futarisIRCcloud: welcome remote contributors! | 09:41 |
| mithro | futarisIRCcloud: tinyfpga-bx | 09:41 |
| mithro | futarisIRCcloud: probably tinyfpga-b2 as well probably because I have one... | 09:42 |
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| futarisIRCcloud | mithro: BX. Shame it's out of stock on little bird / sparkfun Australia. https://www.littlebirdelectronics.com.au/tinyfpga-bx-board | 09:44 |
| mithro | futarisIRCcloud: I could put one in the mail for you.... | 09:45 |
| mithro | Or tinyfpga could :-P | 09:45 |
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| futarisIRCcloud | Cool. I'm really looking forward to the EX series with Type-C USB. | 09:47 |
| mithro | So am I | 10:17 |
| daveshah | We all are :D | 10:19 |
| daveshah | Very happy with my prototype | 10:19 |
| daveshah | Would like to see the CC lines connected though | 10:20 |
| mithro | Yes | 10:21 |
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| mithro | xobs: http://www.vlsitechnology.org/html/libraries.html | 12:14 |
| tpb | Title: Standard Cells, open source (at www.vlsitechnology.org) | 12:14 |
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| xobs | mithro: thanks! | 13:30 |
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| felix_ | hmm, i wonder if it is easily possible to formally verify a design written in litex/migen directly in python without having to poke the generated verilog code | 17:59 |
| mithro | xobs: https://twitter.com/mguthaus/status/968257071857594368 | 20:21 |
| mithro | xobs: Seems up your alley :-P | 20:21 |
| tinyfpga | daveshah: maybe I can pull the CC pins out to testpoints on the bottom, then you can hook them up to one of the IOs on the board | 20:29 |
| tinyfpga | daveshah: I’m using all the IOs I can get out and I suspect most people will not bother with the CC pins due to their complexity | 20:30 |
| daveshah | makes sense | 20:30 |
| daveshah | Might as well do SBU if you have room | 20:30 |
| daveshah | Small pads are fine | 20:30 |
| tinyfpga | daveshah: yeah, I would route them all out | 20:31 |
| tinyfpga | daveshah: I’ll be putting one or two resistors there as well | 20:31 |
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| cr1901_modern | felix_: Not yet... all I can say for now :P | 21:49 |
| cr1901_modern | It'll be easier soon | 21:50 |
| CarlFK | felix_: are you my LCA roommate felix? | 21:50 |
| felix_ | CarlFK: yep | 22:02 |
| felix_ | cr1901_modern: sounds promising | 22:02 |
| CarlFK | felix_: hi! | 22:08 |
| felix_ | hi | 22:10 |
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