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| xobs | If "rc" is a RemoteClient, and csrs are 8-bits, and "reg" is a 32-bit value, what happens if I do "rc.write(rc.regs.reg.addr, 0x12345678)"? | 05:58 |
|---|---|---|
| xobs | Does it write all 32 bits in 8-bit chunks? Does it only write the first or last 8-bits? If it only writes 8 bits, how can I know what other addresses need to be written? | 06:03 |
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| xobs | Hmm... it looks like it doesn't work that way. Maybe I need to use rc.regs.reg.write(0x12345678)? | 10:03 |
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| cr1901_modern | xobs: So I admit it's been a long time since I looked this info up, but RemoteClient communicates over a wishbone bus | 10:52 |
| cr1901_modern | The wishbone master is hardcoded to write 32-bit values: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbonebridge.py#L117 | 10:52 |
| tpb | Title: litex/wishbonebridge.py at master · enjoy-digital/litex · GitHub (at github.com) | 10:52 |
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| cr1901_modern | The gateware has a conversion layer to CSR, looks like it's a direct connection, so only the lower 8-bits of any 32-bit wishbone word are actually attached to the bus | 10:59 |
| cr1901_modern | https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone2csr.py#L7 | 10:59 |
| tpb | Title: litex/wishbone2csr.py at master · enjoy-digital/litex · GitHub (at github.com) | 10:59 |
| cr1901_modern | err, wrong line: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone2csr.py#L20 | 11:00 |
| tpb | Title: litex/wishbone2csr.py at master · enjoy-digital/litex · GitHub (at github.com) | 11:00 |
| cr1901_modern | Each byte of a CSR reg is aligned to a 4 byte boundary | 11:00 |
| cr1901_modern | (Note to self: Ask sb0 why WB2CSR registers the inputs to the CSR portion of the bus) | 11:03 |
| sb0 | to improve timing | 11:03 |
| cr1901_modern | Ahhh | 11:03 |
| cr1901_modern | And I forgot you were in this room :P | 11:04 |
| cr1901_modern | _florent_: https://github.com/enjoy-digital/litex/blob/master/litex/soc/tools/remote/comm_uart.py#L62 | 11:26 |
| cr1901_modern | Sorry for the dumb q, but should this be addr+(offset*4) on this line? B/c offset will be given in 32-bit words, but the wishbone address you write is byte-addressible | 11:26 |
| tpb | Title: litex/comm_uart.py at master · enjoy-digital/litex · GitHub (at github.com) | 11:26 |
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| xobs | cr1901_modern: In my implementation, I had csr_width=32, so I didn't have that issue. But when Bunnie tried, he saw that 32-bit CSRs caused data corruption on HDMI, so he had to go back to 8-bit CSRs, which is when I ran into the issue. | 12:28 |
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| xobs | I'd known that the C code generated accessors that worked right, I just thought the Python code would also work right. It worked better when I used the generated functions rather than the direct addresses... | 12:28 |
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| cr1901_modern | xobs: Well, I'm of the opinion if you need 32-bit accesses, allocate a chunk of address space for a wishbone peripheral. The new address decoding algorithm is smart enough to only allocate what you need. | 12:56 |
| cr1901_modern | I don't know many ppl who use 32-bit CSRs | 12:56 |
| xobs | cr1901_modern: Oh neat, you can have certain CSRs be wider than others? I'm still working on the riscv debug stuff... | 12:58 |
| cr1901_modern | xobs: No, IIRC, your CSR bus width is hardcoded at the SoC level | 12:58 |
| cr1901_modern | what I was saying is that I/O accesses _don't have to take place behind a CSR_ | 12:59 |
| xobs | No? I can have Etherbone access the 32-bit wires without an intermediate CSR? | 12:59 |
| cr1901_modern | Yes | 13:00 |
| cr1901_modern | if you can tolerate doing the wishbone cyc/stb/ack dance for your core, you can just put your peripheral on the wishbone bus if you need variable widths | 13:00 |
| cr1901_modern | Lemme show you an slightly out-of-date example | 13:00 |
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| cr1901_modern | https://github.com/cr1901/ymsoc/blob/master/ymsoc/ym2151.py YMSoC is a MiSoC core I created to test a then-new YM2151 Verilog core. | 13:01 |
| tpb | Title: ymsoc/ym2151.py at master · cr1901/ymsoc · GitHub (at github.com) | 13:01 |
| cr1901_modern | The YM2151 must run at 4MHz or below; easiest thing to do is to just stop the 32MHz CPU for 8 cycles | 13:02 |
| cr1901_modern | until an I/O read/write can be registered | 13:02 |
| cr1901_modern | CSR isn't capable of doing that, so I attached the YM2151 core as a wishbone peripheral w/ wait states | 13:02 |
| cr1901_modern | xobs: Here's how I added it to my core: https://github.com/cr1901/ymsoc/blob/master/ymsoc/core.py#L30 | 13:03 |
| tpb | Title: ymsoc/core.py at master · cr1901/ymsoc · GitHub (at github.com) | 13:03 |
| cr1901_modern | (Yes I also attached it as a CSR device; not relevant here :P, but cores can attach themselves to both the CSR and Wishbone bus without problems) | 13:03 |
| xobs | I see. You just add it as a memory region. | 13:04 |
| cr1901_modern | Yes, it just becomes memory-mapped I/O on the wishbone bus from the SoC's POV | 13:04 |
| xobs | I was noticing some errors when directly communicating with Etherbone, though. For some reason I could only write the lower 16-bits when directly addressing RAM. But perhaps that was an issue with how the DDR controller is attached. | 13:04 |
| cr1901_modern | I've never seen this issue, and tbh I've attached Etherbone (UART) to DRAM exactly once lol | 13:05 |
| * cr1901_modern should really finish that "LiteX tour" blog post | 13:07 | |
| xobs | I do know there are issues with how I deal with Wishbone, because it keeps dropping off Ethernet. I really need to understand Wishbone more. Time to look at timing diagrams some more... | 13:07 |
| cr1901_modern | it's... annoying | 13:08 |
| cr1901_modern | https://www.wdj-consulting.com/ymsoc/intro.html#block-diagram Does this block diagram help at all? | 13:08 |
| tpb | Title: What is YMSoC YMSoC 0.5 documentation (at www.wdj-consulting.com) | 13:08 |
| xobs | Yeah. The good news is that Wishbone itself isn't dying, at least not from what I can tell reading the tea leaves. | 13:09 |
| xobs | Anyway, thank you. This is a huge help. | 13:09 |
| cr1901_modern | Yw :) | 13:09 |
| cr1901_modern | xobs: This is OT, but... you designed the novena, correct? | 13:12 |
| xobs | Bunnie and I, yes. | 13:13 |
| cr1901_modern | This is a stupid question, but IIRC it has a Xilinx FPGA one can play with. How is one supposed to design bitstreams for that on Novena? | 13:13 |
| cr1901_modern | (Or is the answer "you don't"?) | 13:13 |
| cr1901_modern | I don't own one, btw... ENOMONEY | 13:14 |
| xobs | Funnily enough, few people did anything with it. It's a Spartan 6 (LX45 IIRC), which came in handy for reverse-engineering some Mediatek phones and SD cards. | 13:15 |
| xobs | You download Webpack for your x86 machine. | 13:15 |
| cr1901_modern | Hah... where's the fun in that :P? Tbf, if I had a Novena (and patience to do kernel dev- which I don't) I'd put an FM synth core on it. So it'd be like those old home computers like x68k | 13:17 |
| xobs | ...though I did manage to synthesize a bitstream for it once by running Webpack through ExaGear | 13:17 |
| xobs | It took an hour to synthesize and just blinked an LED. | 13:18 |
| cr1901_modern | Well fortunately, looks like some novena users jumped on the ice40 bandwagon and are crowdfunding a new FPGA | 13:23 |
| cr1901_modern | add-on board* | 13:29 |
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| felix_ | rohitksingh: do you have some time and motivation to review the schematics of the axiom photonsdi hw board? https://github.com/felixheld/AXIOM-photonSDI-hw | 16:57 |
| tpb | Title: GitHub - felixheld/AXIOM-photonSDI-hw: SDI interface board for the apertus° AXIOM beta camera (at github.com) | 16:57 |
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| rohitksingh | felix_: Hi! Yup, I'll review it and let you know my feedback | 18:11 |
| felix_ | thx :) | 18:28 |
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| felix_ | rohitksingh: maybe join freenode/#photonsdi to discuss your findings; at least that's the main channel for that project | 18:51 |
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| CarlFK | tumbleweed: can you bump the ppas to bionic? | 22:16 |
| CarlFK | at least I am guessing thats what I need for E: Unable to locate package vizzini-dkms | 22:16 |
| CarlFK | lets see if this breaks anythingapt-add-repository 'deb http://ppa.launchpad.net/timvideos/fpga-support/ubuntu xenial main' | 22:29 |
| tpb | Title: Index of /timvideos/fpga-support/ubuntu (at ppa.launchpad.net) | 22:29 |
| tumbleweed | CarlFK: copied to bionic | 22:45 |
| CarlFK | thankyou! | 22:47 |
| CarlFK | tumbleweed: you create the udev rule twice.. any idea what is going on? https://wiki.debconf.org/wiki/Videoteam/SBC_for_Opsis#Round_3:_Things_stefanor_did | 23:28 |
| tpb | Title: Videoteam/SBC for Opsis - Wiki (at wiki.debconf.org) | 23:28 |
| tumbleweed | no, once is good enough | 23:29 |
| tumbleweed | twice won't break anything | 23:29 |
| CarlFK | lol - I was wondering if the 2nd one should have been soemthing else | 23:31 |
| CarlFK | none of the altys setup made it into ansible, right? | 23:32 |
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