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| xobs | Still poking at VexRiscv debugging. I'm seeing a few oddities, understandably. | 07:53 |
|---|---|---|
| xobs | For one, reset is behaving strangely. When the bios first loads, I can interact with it, but if I reset the softcore, I only get serial output -- typing doesn't yield anything, and CSR_UART_RXTX never changes. Is there some reset sequence I'm not doing? Should I also reset Wishbone, if that's possible? | 07:55 |
| cr1901_modern | xobs: Which dev board? | 07:56 |
| * cr1901_modern wants to know out of curiosity | 07:56 | |
| xobs | cr1901_modern: netv2 (with T100!) | 07:56 |
| cr1901_modern | Hrm, can't help much w/ that I'm afraid. There's been a number of softcore woes collectively in litex lately | 07:57 |
| cr1901_modern | lm32 crashes ice40, vexriscv doesn't work properly w/ Artix | 07:57 |
| cr1901_modern | (and vexriscv has a learning curve b/c they wrote it in a FP lang repurposed for HDL) | 07:58 |
| xobs | It's mostly working. And I'm pretty pleased with how litex laid out. | 07:59 |
| xobs | I've already got a version of Verilog merged upstream that exposes the debug bus. I'm just working on integrating it into litex now. | 08:00 |
| cr1901_modern | I've seen lm32 crash on spartan 6 and spartan 3 a few characters into displaying the banner. But it was consistent- i.e. didn't need to reset it to see the crash. | 08:01 |
| xobs | The problems I'm running into are serial not working on reboot, and Bunnie's HDMI code does something with a PLL that breaks. | 08:02 |
| cr1901_modern | solution was to use a nice power-of-two for the RAM size | 08:02 |
| cr1901_modern | (idk why that works) | 08:02 |
| xobs | The nice thing is that I can connect gdb to the softcore and examine the CSR, which I'd imagine would be updated if a character came in. | 08:02 |
| xobs | Unless there's something weird going on where the reset happens as the softcore is mastering wishbone, and doesn't release the semaphore. Or however it's architected. I should look into that now. | 08:03 |
| cr1901_modern | semaphore? | 08:03 |
| xobs | How does bus mastering work on Wishbone? | 08:04 |
| cr1901_modern | well, in particular for misoc/litex, the only mastering scheme I'm currently aware of is RoundRobin | 08:05 |
| cr1901_modern | (grep for that identifier) | 08:05 |
| cr1901_modern | The caches of the softcore attach to a RoundRobin arbiter in any litex design, and if you have any other cores capable of mastering, it would also attach to the arbiter | 08:06 |
| cr1901_modern | (so minimum of 2 wb bus masters in any design) | 08:07 |
| cr1901_modern | xobs: If you're asking "how does Wishbone spec how bus mastering works", it doesn't :P. It just gives examples on how it can be done | 08:08 |
| cr1901_modern | errr, scrap that last message^ | 08:08 |
| cr1901_modern | xobs: Can you elaborate on your question? Are you asking "how does wishbone decide that a core has control of the bus"? Or "how do multiple wishbone cores share control of the bus"? | 08:09 |
| xobs | cr1901_modern: Right now, I have it set up so resetting the softcore via debug is ORed with the i_reset signal. So if you reset it using a debugger, the softcore just resets right away. | 08:10 |
| xobs | I'm wondering how things like Wishbone handle that. What happens if the reset happens in the middle of a read from a Wishbone device? | 08:11 |
| cr1901_modern | Doesn't specify, AFAIR | 08:12 |
| cr1901_modern | if you look at the wishbone spec diagrams, most of the drawings show the reset signal coming from a "clock and reset generator" IP, with well, only a clock and reset line, that attaches to all the other WB devices | 08:13 |
| cr1901_modern | I suppose you could "feed back" information about current bus activity to your clock-reset IP, so if a reset request is received during a read in progress, the reset doesn't trigger until CYC/STB is released | 08:14 |
| cr1901_modern | (Also, are you simulating :)?) | 08:15 |
| xobs | I'm not simulating. That might be a good idea. | 08:16 |
| cr1901_modern | https://github.com/cr1901/ymsoc/tree/master/build/sim Feel free to use this as a starting point if you wish (I'm not familar w/ litex' extra simulation features) | 08:17 |
| tpb | Title: ymsoc/build/sim at master · cr1901/ymsoc · GitHub (at github.com) | 08:17 |
| xobs | It's kinda fun that I can poke values into the CSR from the CPU using gdb and cause it to print values to the serial port. | 08:56 |
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