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| cr1901_modern | mithro, daveshah: Well, this is about as bad of a bug as it gets; simulation says that lm32 on tinyfpga shouldn't be crashing. | 01:44 |
|---|---|---|
| cr1901_modern | or icebreaker* | 01:44 |
| cr1901_modern | but of course in reality, it does crash | 01:44 |
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| mithro | cr1901_modern: :-( | 01:47 |
| mithro | cr1901_modern: Timing bug? | 01:47 |
| cr1901_modern | mithro: It's possible, but I have plenty of timing margin. It crashes on the first jump. I guess my next step is to wrap litescope around the design | 01:50 |
| cr1901_modern | The only "good" thing about this is that the crash is deterministic | 01:51 |
| cr1901_modern | (Or alternatively, I could create a single stepper circuit) | 01:56 |
| mithro | cr1901_modern: Will be interesting to find out why it is failing... | 02:12 |
| mithro | cr1901_modern: You might have seen that I'm trying to get icestorm and arachne-pnr into conda | 02:17 |
| cr1901_modern | That should be a relatively well-behaved package | 02:18 |
| mithro | cr1901_modern: I want it for the symbiflow-arch-defs | 02:24 |
| mithro | cr1901_modern: For now I had to disable iceprog as it needs libusb and libftdi and I didn't want to put them in a deps at the moment | 02:24 |
| cr1901_modern | Well I think iceprog only works w/ relatively few boards anyway? | 02:38 |
| mithro | cr1901_modern: Dunno... | 02:51 |
| * cr1901_modern is breaking out part of lm32's addr bus and hoping timing passes | 02:52 | |
| cr1901_modern | mithro: Well, I found _something_ that's definitely a simulation/synthesis mismatch | 03:55 |
| cr1901_modern | https://imgur.com/a/5Q1QfB9 | 03:58 |
| tpb | Title: TinyFPGA LM32 Waveforms - Album on Imgur (at imgur.com) | 03:58 |
| mithro | cr1901_modern: You can make litescope output sigrok traces IIRC.... | 04:03 |
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| daveshah | cr1901_modern: this really is weird | 06:37 |
| daveshah | Because is was crashing in Icecube2 also, so not an icestorm issue | 06:37 |
| _florent_ | cr1901_modern: lm32 was working some months ago on the tinyfpga using icestorm, are you doing something different than what what we where doing some months ago? | 07:44 |
| _florent_ | cr1901_modern: if you want i can check if it's still working | 07:44 |
| cr1901_modern | _florent_: If you can create a minimal example that works, please do | 08:13 |
| cr1901_modern | But right now I don't have the bandwidth to check myself | 08:14 |
| cr1901_modern | For all I know, we stumbled upon an edge case in the Verilog spec that Xilinx/iverilog can handle, but yosys/icecube can't | 08:15 |
| cr1901_modern | (although IIRC icecube uses synopsys, which I think Xilinx might use?) | 08:15 |
| daveshah | anyway LM32 is made by *Lattice* | 08:24 |
| daveshah | it should work on their own tools | 08:24 |
| daveshah | but maybe it's actually a Migen/LiteX issue | 08:24 |
| cr1901_modern | daveshah: Tbf, ice40 was an acquisition from SiliconBlue | 08:37 |
| daveshah | yeah, but the synthesis options are now the same - Synplify or LSE - as Diamond/proper Lattice | 08:37 |
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