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rohitksingh_work | mithro: ping | 03:50 |
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mithro | shenki: I'm around now | 06:04 |
shenki | mithro: hello! | 06:09 |
shenki | mithro: did you see my question from ~18 hours ago? | 06:10 |
mithro | shenki: Yes, let me finish getting stuff ready for Rohit | 06:10 |
mithro | shenki: Did you see that Rusty forwarded a bunch of stuff? | 06:45 |
mithro | shenki: so Rohit should be all sorted now, so if you want help with the irq stuff I have a little time now... | 06:50 |
shenki | mithro: okay. can you answer the questions from yesterday? | 06:51 |
mithro | Possibly | 06:51 |
mithro | So, firstly each peripheral has their own "event manager" | 06:52 |
mithro | The output of the event managers are logically anded together and wired to the irq pin | 06:55 |
mithro | shenki: the event manager interface is described in LiteX here -> https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/csr_eventmanager.py | 06:57 |
tpb | Title: litex/csr_eventmanager.py at master · enjoy-digital/litex · GitHub (at github.com) | 06:57 |
mithro | shenki: so my first question is what makes you think the irq you got is for the ethernet and not the UART or other peripheral? | 07:00 |
shenki | it triggers when i run the ping command | 07:00 |
shenki | but not when I type other characters, nor press buttons | 07:00 |
shenki | if i don't enable it, it doesn't fire | 07:01 |
shenki | and packets don't get sent from the device | 07:01 |
mithro | And which interrupt are you looking at? | 07:01 |
shenki | 3 | 07:01 |
mithro | https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/arty/net.py#L34 | 07:03 |
tpb | Title: HDMI2USB-litex-firmware/net.py at master · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com) | 07:03 |
mithro | https://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/mac/__init__.py | 07:05 |
tpb | Title: liteeth/__init__.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 07:05 |
mithro | Which seems to go here | 07:07 |
mithro | https://github.com/enjoy-digital/liteeth/blob/master/liteeth/core/mac/wishbone.py | 07:07 |
tpb | Title: liteeth/wishbone.py at master · enjoy-digital/liteeth · GitHub (at github.com) | 07:07 |
mithro | Which goes to this bit which has the event manager... | 07:07 |
mithro | shenki: got a link to your code? | 07:09 |
mithro | shenki: have you looked at this code? https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/firmware/uip/liteethmac-drv.c#L54 | 07:11 |
tpb | Title: HDMI2USB-litex-firmware/liteethmac-drv.c at master · timvideos/HDMI2USB-litex-firmware · GitHub (at github.com) | 07:12 |
shenki | yes | 07:12 |
shenki | mithro: http://ozlabs.org/~joel/litex_liteeth.c | 07:12 |
shenki | the commented out rx code in liteeth_interrupt doesn't work. but if you run that code, it does send ARP requests over the wire | 07:13 |
shenki | if you move the #if 0 down to below the two ioread8's, you will get lots of 0's | 07:14 |
shenki | ie, the WRITER_EV_STATUS and READER_EV_STATUS always show zero | 07:14 |
mithro | Where did you get the gateware from? | 07:15 |
shenki | i'm running the litex-linux branch | 07:15 |
mithro | You built it yourself? | 07:15 |
shenki | 41ddae5085beb36602be41500f0f314affe499eb with the LEDs reenabled | 07:15 |
shenki | yes | 07:15 |
mithro | You built it yourself? | 07:16 |
mithro | opps | 07:16 |
mithro | You sure you are reading the right memory location? | 07:16 |
shenki | Yes | 07:16 |
mithro | Can you add an ioread+print of the LITEETH_EV_PENDING registers? | 07:18 |
shenki | they show zero also | 07:18 |
shenki | as do the ev_enable regs | 07:18 |
mithro | Well the status registers are likely to always read zero | 07:19 |
mithro | As they are instantaneous... | 07:19 |
shenki | okay | 07:20 |
shenki | the pending registers are zero too, but shouldn't they tell me what the event type was? | 07:20 |
mithro | shenki: Yes, they should I think... | 07:21 |
shenki | okay. how do we work out why that is? | 07:21 |
mithro | shenki: Which makes me think you are reading either from the wrong location or the wrong byte | 07:21 |
shenki | okay. i'm reading the length register incorrectly. I now understand the point _florent_ was making about the byte accesses | 07:23 |
mithro | https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.3-1077-g6747572/arty/net/or1k/software/include/generated/csr.h | 07:23 |
tpb | Title: HDMI2USB-firmware-prebuilt/csr.h at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com) | 07:23 |
mithro | shenki: https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.3-1077-g6747572/arty/net/or1k/software/include/generated/csr.h#L54-L63 | 07:23 |
tpb | Title: HDMI2USB-firmware-prebuilt/csr.h at master · timvideos/HDMI2USB-firmware-prebuilt · GitHub (at github.com) | 07:23 |
shenki | i can't see how that would accidently touc hthe pending registers | 07:23 |
mithro | The csr register read/writes are a bit funky because it's a 8bit wide bus mapped onto a 32bit wide bus | 07:24 |
mithro | shenki: Are you reading from the wrong end of the 32bit wide (IE big endian verse small endian?) | 07:24 |
shenki | no | 07:25 |
shenki | I'm doing single byte reads | 07:25 |
shenki | so that can't be it | 07:25 |
mithro | shenki: But which byte are you reading? | 07:26 |
mithro | iowrite8 only reads one byte right? | 07:26 |
shenki | correct | 07:28 |
mithro | So priv->base is something like 0xe0008000 ? | 07:28 |
shenki | yes | 07:28 |
shenki | mac0: mac@e0007800 { | 07:29 |
shenki | compatible = "litex,liteeth"; | 07:29 |
shenki | reg = <0xe0008000 0x44 | 07:29 |
shenki | 0xe0007800 0x0a | 07:29 |
shenki | 0xb0000000 0x2000>; | 07:29 |
shenki | interrupts = <3>; | 07:29 |
shenki | tx-fifo-depth = <2>; | 07:29 |
shenki | rx-fifo-depth = <2>; | 07:29 |
shenki | }; | 07:29 |
mithro | shenki: Notice how each CSR value which is 1 byte wide actually goes up by 4? | 07:30 |
mithro | shenki: Can you try reading all those 4 bytes? | 07:33 |
shenki | which four bytes? | 07:34 |
mithro | shenki: 0x38, 0x39, 0x3a 0x3b | 07:35 |
mithro | and | 07:35 |
mithro | shenki: 0x18, 0x19, 0x1a, 0x1b | 07:36 |
mithro | (First one being LITEETH_READER_EV_PENDING and the second one being LITEETH_WRITER_EV_PENDING) | 07:36 |
mithro | Also what are you writing to LITEETH_WRITER_EV_ENABLE ? | 07:37 |
_florent_ | shenki: if you receive the interrupts, that's really strange you don't see anything in pending | 07:52 |
_florent_ | shenki: like mithro, i really think you have to double check you are reading the registers correctly | 07:53 |
_florent_ | shenki: if you are receiving the irq, enable should be set correctly | 08:01 |
_florent_ | shenki: this driver uses pending register for the writer: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/software/libuip/liteethmac-drv.c | 08:02 |
tpb | Title: liteeth/liteethmac-drv.c at master · enjoy-digital/liteeth · GitHub (at github.com) | 08:02 |
mithro | shenki: I'm thinking of heading home / to bed soon | 08:09 |
_florent_ | shenki: in your code, don't use LITEETH_READER_EV_STATUS/LITEETH_WRITER_EV_STATUS | 08:12 |
_florent_ | shenki: but only the EV_PENDING | 08:12 |
_florent_ | shenki: now first thing to fix: if you write 1 to LITEETH_WRITER_EV_ENABLE and don't read 1 from it, there is clearly an issue with your csr access function, no need to go further without fixing that. | 08:14 |
shenki | _florent_: thanks for the tips. I'll take a close look at it now | 10:10 |
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shenki | hrm. can't work out what's going on | 12:41 |
shenki | [ 723.770000] liteeth e0008000.mac eth0: writer bc008018 00 | 12:41 |
shenki | [ 725.760000] liteeth e0008000.mac eth0: reader bc008038 00 | 12:41 |
shenki | I pushed the tree to litex/liteeth-wip at https://github.com/shenki/linux if anyone else wants to try | 12:41 |
tpb | Title: GitHub - shenki/linux: Linux kernel source tree (at github.com) | 12:41 |
shenki | https://github.com/shenki/linux/commits/litex/liteeth-wip | 12:41 |
tpb | Title: Commits · shenki/linux · GitHub (at github.com) | 12:41 |
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shenki | ah. MMPTR does a four byte read (it casts the pointer to an int), and the csr.h implicitly casts to a u8, discarding the top three bytes | 13:09 |
shenki | so if i change all of my ioread8's to ioread32be, the code Just Works | 13:09 |
shenki | 🔥 | 13:10 |
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mithro | shenki: \o/ | 18:00 |
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CarlFK[m] | mithro: What all was I spozed to do for you when I had time? | 18:39 |
mithro | CarlFK[m]: test the latest builds and figure out what is going on | 18:39 |
CarlFK[m] | also poke you about visa paperwork or something like that | 18:41 |
CarlFK[m] | which reminds me - I think I need to do something for me along those lines | 18:41 |
mithro | CarlFK[m]: visa paperwork is all done last night | 18:41 |
CarlFK[m] | yay! whatever it was :p | 18:42 |
mithro | Trying to get Rohit into Australia | 18:42 |
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CarlFK[m] | that's right | 18:51 |
mithro | LCA FPGA Miniconf sign up is now open - get in before we start advertising it! | 20:00 |
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