Friday, 2017-11-10

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Ishan_Bansalmithro : ping05:42
mithroIshan_Bansal: Pong!05:43
mithroIshan_Bansal: I'm actually in America at the moment05:43
Ishan_Bansalmithro : Oh cool, I saw your post for moving to US05:43
Ishan_Bansalmithro : Do you have time to see the Huffman encoder today ?05:44
mithrohttps://github.com/k88hudson/git-flight-rules05:49
tpbTitle: GitHub - k88hudson/git-flight-rules: Flight rules for git (at github.com)05:50
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CarlFK[m]https://opensource.com/article/17/9/equipment-recording-presentations16:19
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cr1901_modernmithro: TinyFPGA works in migen now. Waiting for rjo to merge my current PR improving icestorm before adding it to Litex.17:24
ysionneaucr1901_modern: you support only TinyFPGA B2?17:25
cr1901_modernysionneau: Correct17:26
cr1901_modernthere is no B1, and I don't think the A-series FPGAs are supported in Migen at all17:26
ysionneauyep ok17:27
ysionneauwhich kind of design do you run on this board?17:27
ysionneaucan you run a small SoC?17:27
cr1901_modernThat's what I want to find out next17:27
cr1901_modernit's not gonna run the default lm3217:27
ysionneauI think I tried to synthesize a small SoC on P8K device in 2015 but it was very small17:27
mithroysionneau: Trying to replicate https://lab.whitequark.org/notes/2016-10-19/implementing-a-simple-soc-in-migen/17:28
tpbTitle: Implementing a simple SoC in Migen — whitequarks lab notebook (at lab.whitequark.org)17:28
cr1901_modernwhitequark was able to do mor1k on hx8k17:28
cr1901_modernYea, like that17:28
ysionneauoh mor1kx, nice, it's bigger than lm32 I think isn't it?17:28
cr1901_modernIt's not gonna run the default lm32 b/c lm32_config.v provided by misoc uses a hardware multiplier17:29
ysionneauyep sure17:29
cr1901_modernand probably too much block RAM for cache17:29
ysionneauyou need to trim it down a bit17:29
ysionneaumithro: very cool, this proves it's definetely possible, nice!17:30
cr1901_modernysionneau: mithro also wants to try micropython on it17:30
mithro-- https://github.com/mithro/litex/blob/cpu-config/litex/soc/cores/cpu/mor1kx/core.py17:30
tpbTitle: litex/core.py at cpu-config · mithro/litex · GitHub (at github.com)17:30
mithrohttps://github.com/mithro/litex/blob/cpu-config/litex/soc/cores/cpu/lm32/core.py17:31
tpbTitle: litex/core.py at cpu-config · mithro/litex · GitHub (at github.com)17:31
mithroThat is my initial attempt to start making CPU objects more configurable...17:31
ysionneauah, to integrate nicely with the special verilog bloc instanciation + all the software implications (linker and compiler flags)17:33
mithrohttps://docs.google.com/document/d/1J8gmL6sasN8b3gZHkUw03gIBYeeteWHtUmERV75vI54/edit#17:33
tpbTitle: MiSoC / LiteX "CPU Configs" - Google Docs (at docs.google.com)17:33
cr1901_modernmithro: Maybe I misunderstood, but I thought there were talks to merge litex back into misoc17:35
cr1901_modernor at least to trim litex down to "misoc extensions"17:35
mithrocr1901_modern: That is the long term plan17:37
cr1901_modernmithro: Okay, so I think therefore it still makes sense for me to get my new platforms, etc into migen and then make them run on Litex. I'm gonna try a _misoc_ cpu today hopefully17:39
mithroGreat17:43
cr1901_modernafter that I'll take a look into micropython... as well as doing a USB device in migen17:45
cr1901_modern(because I want to. It's time for me to stop fearing USB)17:45
cr1901_modernmithro: https://github.com/m-labs/migen/pull/84 https://github.com/m-labs/migen/pull/8518:26
cr1901_modernIf you wish to play w/ TinyFPGA early, you can use the changes here, but they are subject to change18:26
tpbTitle: Icestorm Backend Improvements by cr1901 · Pull Request #84 · m-labs/migen · GitHub (at github.com)18:27
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CarlFK[m]mithro (IRC): https://veyepar.nextdayvideo.com/static/temp/relay_wires.svg19:02
CarlFK[m]did you see that? next day or two would be a good time to actually wire it up and get it working19:03
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