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| paddatrapper | mithro: I've had no Internet for about the past week, but hope to get somewhere by the end of the week | 03:42 |
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| paddatrapper | CarlFK: they are called system facts. A full list is here: http://docs.ansible.com/ansible/playbooks_variables.html#information-discovered-from-systems-facts | 03:44 |
| tpb | Title: Variables Ansible Documentation (at docs.ansible.com) | 03:44 |
| CarlFK | paddatrapper: thanks - knowing the right terms helps | 04:43 |
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| mithro | tumbleweed: Ping me when you are in Hamburg :-) | 11:15 |
| tumbleweed | mithro: ack. I land at 3 | 11:18 |
| mithro | tumbleweed: Where are you staying? | 11:45 |
| tumbleweed | mithro: an airbnb, fairly near by | 11:59 |
| mithro | I'm at the Marriott | 12:01 |
| tumbleweed | ok, I think that's in the opposite direction, but still pretty close | 12:04 |
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| mithro | cr1901_modern: ping? | 15:27 |
| cr1901_modern | mithro: pong | 15:28 |
| mithro | cr1901_modern: How's things going? | 15:28 |
| cr1901_modern | mithro: I'm kinda stuck. I'm reflashing the scope firmware and I'll play with an IPython notebook. | 15:29 |
| mithro | I've been thinking about if having gdb support would help | 15:30 |
| cr1901_modern | mithro: It may very well help, but something else is bothering me | 15:31 |
| cr1901_modern | mithro: LM32 has a cache. It should be caching everything read from flash | 15:35 |
| cr1901_modern | Why would a value read from cache be different when its read a second time? | 15:35 |
| mithro | cr1901_modern: no idea | 15:35 |
| cr1901_modern | mithro: Is the ROM section uncached? | 15:36 |
| mithro | cr1901_modern: NFI.... | 15:36 |
| cr1901_modern | I may need to simulate parts of the CPU in iverilog. | 15:38 |
| mithro | cr1901_modern: https://github.com/enjoy-digital/litex/pull/14 | 15:47 |
| tpb | Title: spi_flash: fix bitbang with spi_width=1 by mithro · Pull Request #14 · enjoy-digital/litex · GitHub (at github.com) | 15:47 |
| mithro | cr1901_modern: There is a "sim" target which uses verilator | 15:47 |
| cr1901_modern | mithro: Re: that pull request... I'm not sure it works. For 1-bit width, I think the MiSoC fix doesn't send the data down miso | 15:49 |
| mithro | cr1901_modern: Can you put a comment on it | 15:49 |
| cr1901_modern | mithro: Done. (Albiet poorly formatted) | 15:58 |
| ysionneau | cr1901_modern: what's your problem with lm32 exactly ? | 18:47 |
| mithro | [mithro/HDMI2USB-litex-firmware/nextgen#60] (d801073): The build passed. (https://travis-ci.org/mithro/HDMI2USB-litex-firmware/builds/186816186) | 19:29 |
| mithro | ysionneau: He is trying to get the bios to boot from spi flash directly | 19:29 |
| mithro | _florent_: ping? | 19:56 |
| mithro | _florent_: Currently got access to a NeTV2 board and trying to get the BaseSoC to boot | 19:56 |
| ysionneau | mithro: is he sure that what he reads from flash is correct first? | 20:22 |
| ysionneau | he can try booting a small BIOS from blockram and then do mr to read the flash from the bios cmd line | 20:22 |
| mithro | ysionneau: We just use the wishbone uart bridge to read the spi flash | 20:27 |
| mithro | ysionneau: That was returning the contents expected | 20:27 |
| ysionneau | hmmm ok, weird | 20:29 |
| ysionneau | is the code on some github branch? | 20:30 |
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| mithro | ysionneau: I can forward what I sent cr1901 | 20:47 |
| ysionneau | mithro: yep I can have a look :) | 20:47 |
| mithro | ysionneau: email sent | 20:49 |
| ysionneau | got it thx ! | 20:50 |
| mithro | ysionneau: Oh and https://github.com/enjoy-digital/litex/pull/14/commits/e39c470bbc627212f394f528a0b1943b83cc7809 | 20:55 |
| tpb | Title: spi_flash: fix bitbang with spi_width=1 by mithro · Pull Request #14 · enjoy-digital/litex · GitHub (at github.com) | 20:55 |
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| CarlFK | Why would a value read from cache be different .... Can the cache be disabled to see if that fixes things? (hoping this is easy to try and easy to see results) | 22:22 |
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