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shenki | mithro: how do irqs work on the lm32? | 23:28 |
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shenki | trying to get my head around how both the bios and the firmware can recieve irqs, when one is loaded at 0 and the other is loaded into ram | 23:29 |
mithro | shenki: NFI - however | 23:31 |
mithro | libbase/crt0-or1k.S | 23:31 |
mithro | 107: /* external interrupt */ | 23:31 |
mithro | libbase/crt0-lm32.S | 23:31 |
mithro | 90:_interrupt_handler: | 23:31 |
shenki | yeah | 23:31 |
shenki | so how does that ever get called when you've jumped into the firmware, which is loaded up at 0x.... whatever DRAM is | 23:32 |
mithro | I'm guessing two options | 23:32 |
mithro | BIOS has a forwarding interrupt handler | 23:32 |
mithro | BIOS does some type of patching | 23:32 |
mithro | shenki: ask on #m-labs - they will know | 23:32 |
shenki | okay | 23:33 |
shenki | mithro: is the whole bios + firmware setup something that all the devices do? | 23:34 |
mithro | shenki: What do you mean? | 23:35 |
mithro | shenki: Really, the bios isn't needed on boards which don't have DDR ram | 23:35 |
shenki | mithro: how we have a bios that chainloads to a firmware | 23:35 |
shenki | ok | 23:35 |
shenki | i just asked the question in #m-labs. it didn't sound very intelligent, so feel free to jump in and clarify | 23:36 |
mithro | shenki: But I'm pretty sure neither _florent_ nor m-labs peeps are using boards without DDR | 23:36 |
shenki | ok | 23:39 |
cr1901_modern | minispartan is SDRAM I believe? | 23:50 |
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