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| mithro | xfxf: ping? | 03:35 |
|---|---|---|
| xfxf | mithro: pong. haven't progressed much this week due to day job taking up most of my awake time, working all of this w/e on AV things | 03:37 |
| xfxf | will you be around? | 03:38 |
| mithro | xfxf: I hope to be, but no guarantees | 03:38 |
| xfxf | that's fine | 03:38 |
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| mithro | ssk1328: ping? | 04:42 |
| nueces | hola! | 04:50 |
| nueces | today I connected the hdmi output from my computer to the opsis, input 0 | 04:50 |
| nueces | the xrandr found it, but the opsis don't get any input | 04:51 |
| nueces | http://dpaste.com/0YZGBPM | 04:51 |
| tpb | Title: dpaste: 0YZGBPM (at dpaste.com) | 04:51 |
| nueces | any ideas? | 04:52 |
| mithro | nueces: what does the debug output show? | 04:52 |
| mithro | nueces: what type of cable are you using? | 04:52 |
| nueces | mithro, could you remember me how to use the debug? | 04:53 |
| nueces | :( | 04:53 |
| mithro | nueces: IIRC "debug input0" ? | 04:53 |
| nueces | http://dpaste.com/0X2VKVZ | 04:54 |
| tpb | Title: dpaste: 0X2VKVZ (at dpaste.com) | 04:54 |
| nueces | the cable is not powered | 04:54 |
| mithro | The WER is the problem | 04:55 |
| nueces | mithro, it should be zero? | 04:59 |
| mithro | nueces: It won't be until after PyCon AU before we add a bunch of stuff which will help you figure out the WER problem | 04:59 |
| nueces | other thing the gnome display tool show the board as a OHW 9" | 04:59 |
| mithro | nueces: Hrm? | 05:00 |
| mithro | nueces: got a screenshot? | 05:00 |
| ssk1328 | mithro: pong | 05:03 |
| nueces | mithro, http://img.ctrlv.in/img/16/07/29/579ae278e6e86.png | 05:04 |
| mithro | ssk1328: So, were are we at? | 05:04 |
| ssk1328 | mithro: This week's report (not very complete) added on the doc | 05:04 |
| mithro | ssk1328: yes, I had a read of it | 05:04 |
| ssk1328 | mithro: I addded a video of dynamic fade I omplemented | 05:04 |
| nueces | (i connected a second input now, as it show in the console) | 05:04 |
| mithro | ssk1328: Yes, I saw - looks pretty cool | 05:05 |
| ssk1328 | mithro: Yeah! First output of my own mixer :) | 05:05 |
| mithro | ssk1328: Is this the "two input / one output" type structure as in https://docs.google.com/document/d/1g1c2IwCVxVzSHWdXbZ746HP-fnM4y1WqFuBZNkLi5mw/edit ? | 05:05 |
| tpb | Title: Mixer Block Design - Google Docs (at docs.google.com) | 05:05 |
| mithro | ssk1328: I realise now that we should have concentrated on this side first and left the RLE stuff till after this was working | 05:06 |
| mithro | nueces: It is worth using xrandr --xprops to look at the edid and see what is there | 05:06 |
| ssk1328 | mithro: yeah! | 05:07 |
| ssk1328 | mithro: I have implemented the two input / one output type structure | 05:07 |
| mithro | ssk1328: What needs to be done to fix the timing problem? | 05:08 |
| nueces | --xprops is an unrecognized option | 05:09 |
| nueces | http://dpaste.com/0QWEDJQ | 05:10 |
| tpb | Title: dpaste: 0QWEDJQ (at dpaste.com) | 05:10 |
| nueces | --prop | 05:10 |
| ssk1328 | mithro: I am not really sure, may need to run some changes in the gateware code | 05:11 |
| ssk1328 | mithro: Maybe incorrect implementation of ack or stb somewhere | 05:11 |
| mithro | nueces: That EDID block seems weird | 05:12 |
| ssk1328 | mithro: Did you see the pics? Maybe you could have seen something like that before? | 05:14 |
| nueces | I'm going to use the prebuild firmware and back later | 05:14 |
| mithro | ssk1328: Yes, I've seen that style of thing before | 05:15 |
| ssk1328 | mithro: So you might know the exact reason why this happens? | 05:16 |
| ssk1328 | mithro: As in the exactly what kind of timing issues | 05:16 |
| mithro | ssk1328: There are a number of different causes | 05:16 |
| nueces | mithro, http://dpaste.com/1G7M5DD this is the version that I'm using now | 05:16 |
| tpb | Title: dpaste: 1G7M5DD (at dpaste.com) | 05:16 |
| mithro | ssk1328: I think it occurs when the pixel data is being delivered at the wrong time | 05:18 |
| mithro | ssk1328: but it could also mean the hsync/vsync signals are being sent incorrectly | 05:18 |
| ssk1328 | mithro: Okay! | 05:18 |
| mithro | ssk1328: It could be something like changing the frame buffer pointer at the wrong time | 05:19 |
| ssk1328 | mithro: Also both the outputs (both the inputs of mixer block) aren't in sync with each other | 05:19 |
| mithro | ssk1328: _florent_ might be able to show more insight | 05:19 |
| mithro | ssk1328: Sure - the frame buffer helps you fix that right? | 05:19 |
| ssk1328 | mithro: As in they are lagging by different times | 05:19 |
| mithro | ssk1328: Yes the inputs are going to be offset from each other in time | 05:20 |
| mithro | ssk1328: but they should be writing frames into the memory | 05:20 |
| mithro | ssk1328: so you can read the two buffers from the memory in sync | 05:21 |
| ssk1328 | Yeah, so I was reffereing to the output at memory before mixer block | 05:21 |
| ssk1328 | mithro: Which are input to mixer block | 05:21 |
| ssk1328 | mithro: They arent in sync as seen in the pattern pic as well | 05:21 |
| ssk1328 | mithro: You stop two different HDMI2USB texts | 05:22 |
| mithro | ssk1328: Hrm? | 05:22 |
| ssk1328 | https://photos.google.com/share/AF1QipOJ0tE656GhYkF4sU3jD3PExuONIAmLrsQplsSLk78PwWPl-T7Tiq2Zrjfm-xqUYw/photo/AF1QipNafs1QhqLUtgIO-b6h2-qeunbj15bhP7EiTldZ?key=RGVxV2tleUdWQVdEV0k2cTZHWGFMUk10Sy1vODB3 | 05:22 |
| mithro | ssk1328: How are you feeding this? | 05:23 |
| ssk1328 | *spot, not stop | 05:23 |
| mithro | ssk1328: Are you using two DMA engines to get the memory buffers out of memory? | 05:23 |
| ssk1328 | I added my modules in the output video pipeline | 05:24 |
| ssk1328 | https://github.com/ssk1328/HDMI2USB-misoc-firmware/blob/float-arithmetic/gateware/hdmi_out/phy.py#L256 | 05:24 |
| tpb | Title: HDMI2USB-misoc-firmware/phy.py at float-arithmetic · ssk1328/HDMI2USB-misoc-firmware · GitHub (at github.com) | 05:24 |
| mithro | ssk1328: The lines around 305 could be the cause of the alignment problem | 05:26 |
| mithro | ssk1328: I don't get how you are getting two pixels into this? | 05:27 |
| ssk1328 | mithro: Yeah so I add some more code in opsis.py and call each of hdmi_out0 and hdmi_out1 class | 05:27 |
| ssk1328 | *opsis_video.py | 05:28 |
| ssk1328 | https://github.com/ssk1328/HDMI2USB-misoc-firmware/blob/float-arithmetic/targets/opsis_video.py#L47 | 05:28 |
| tpb | Title: HDMI2USB-misoc-firmware/opsis_video.py at float-arithmetic · ssk1328/HDMI2USB-misoc-firmware · GitHub (at github.com) | 05:28 |
| mithro | ssk1328: Okay, so it looks like you are just connecting both hdmi outputs together here | 05:30 |
| ssk1328 | mithro: Yeah, I am putting the mult outputs of both the hdmi blocks into two of the add input | 05:31 |
| mithro | ssk1328: So looking at https://github.com/ssk1328/HDMI2USB-misoc-firmware/blob/float-arithmetic/gateware/hdmi_out/__init__.py#L13 | 05:32 |
| tpb | Title: HDMI2USB-misoc-firmware/__init__.py at float-arithmetic · ssk1328/HDMI2USB-misoc-firmware · GitHub (at github.com) | 05:32 |
| mithro | ssk1328: We need to split the DMA and Driver parts | 05:33 |
| ssk1328 | mithro: Okay, we are doing this for solving the alignement problem right? | 05:34 |
| mithro | ssk1328: We need the two DMA modules to deliver the same pixel value to the Driver at the same time | 05:35 |
| ssk1328 | mithro: Okay, so instead of taking the second pixel stream from output1, I will add a nother DMA port at output0 and take the second pixel stream for mixer from there | 05:37 |
| mithro | ssk1328: Yes | 05:38 |
| mithro | ssk1328: I'm just wondering how you keep the two DMA engines in sync | 05:38 |
| ssk1328 | mithro: Another thought, In the final version If I have all the outputs running then we should have 4 DMA ports instead of 2, demanding double the bandwidth, do we have such kind of available bandwidth? | 05:39 |
| mithro | ssk1328: I think we want a single "FrameInitiator / VTG" module which two DMA ports are slaved too | 05:39 |
| mithro | ssk1328: We only have 3 possible inputs, so we only actually need 3 possible DMA engines | 05:40 |
| ssk1328 | mithro: Okay, so the bandwidth remains the same | 05:41 |
| mithro | ssk1328: Notice in the "Three input, 2 output" we have 3 DMA inputs | 05:41 |
| ssk1328 | mithro: Yes | 05:41 |
| mithro | ssk1328: I added some extra stuff to the diagram just then | 05:44 |
| mithro | ssk1328: I think it kind of works like this... | 05:44 |
| ssk1328 | mithro: Just looking at it | 05:45 |
| mithro | ssk1328: I think the FrameInitiator is what generates the in-memory address for each pixel? | 05:45 |
| ssk1328 | mithro: Yeah, the csr functions also have a fi in them | 05:46 |
| mithro | hrm - the FrameInitiator seems to be connected to the VTG | 05:48 |
| ssk1328 | Yes, and then VTG to Driver | 05:50 |
| mithro | so it seems that the FrameInitator and DMA both feed into the VTG which then feeds the output driver... | 05:50 |
| mithro | Don't know if it is a feed or pull structure though.... | 05:50 |
| mithro | be back in 30 - meeting | 05:50 |
| ssk1328 | mithro: Okay | 05:52 |
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| nueces | mithro, http://dpaste.com/1VZ4793 in all the cases the display is detected as OHW 9", the edid seams to be the same for the unstable/testing/stable prebuild firmware | 06:31 |
| tpb | Title: dpaste: 1VZ4793 (at dpaste.com) | 06:31 |
| nueces | mithro, there is a updated list of know cameras that works with the board? | 06:31 |
| nueces | thanks and god night (time to sleep for me) | 06:32 |
| mithro | nueces: Someone needs to work on the EDID a bit I think | 06:33 |
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