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| ssk1328 | mithro: ping? | 05:03 |
|---|---|---|
| mithro | ssk1328: pong | 05:04 |
| ssk1328 | mithro: I updated the weekly report for this week | 05:04 |
| mithro | okay | 05:04 |
| mithro | ssk1328: I'm not sure I have time for the face-to-face, shall we do it via IRC? | 05:05 |
| ssk1328 | mithro: No problem | 05:05 |
| mithro | ssk1328: where are we at? | 05:05 |
| ssk1328 | mithro: I had updated most of the float16 related work in two of the pull requests | 05:06 |
| ssk1328 | mithro: In the float conversion thing, I have added the lookup table implementation for int8 to float16 conversion. | 05:07 |
| ssk1328 | mithro: In the float arithmetic I have added the float add module, tested to work in migen simulation environment. | 05:08 |
| mithro | ssk1328: okay, and where is the CSR stuff? | 05:08 |
| ssk1328 | mithro: Didn't get time to move forward with that | 05:09 |
| ssk1328 | mithro: But I have a vague idea why that didn't work which I will test today | 05:10 |
| mithro | ssk1328: okay | 05:14 |
| ssk1328 | mithro: There are also some other errors that I am facing while porting to litex environment | 05:15 |
| ssk1328 | Which I had mentioned in my pull request comments | 05:15 |
| mithro | ssk1328: what are they? | 05:15 |
| ssk1328 | mithro: I get this when I port the float arith migen code to litex | 05:17 |
| ssk1328 | http://paste.ubuntu.com/19005357/ | 05:17 |
| tpb | Title: Ubuntu Pastebin (at paste.ubuntu.com) | 05:17 |
| ssk1328 | From my understanding, somewhere in the streamer something is not defined as a Signal object, which is causing this error. | 05:17 |
| shenki | mithro: good afternoon | 05:50 |
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| cr1901_modern | mithro: This is a stupid question, but does HDMI guarantee that the RGB signals will be stable a certain amount of time before the pixel clock's leading edge? | 11:20 |
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| cr1901_modern | I've just been thinking: No matter how hard we try, the 10x's pixel clock and the 1x's clock are never going to be COMPLETELY in phase with each other. Suppose the 10x's clock transitions a tiny amount (a few ps) before the 1x's clock. Won't there be a setup-time violation for shifting into the 1x's clock domain (b/c the 10x's clock clocked a new shift register output too early and 1x's hasn't latched the value yet)? | 11:28 |
| cr1901_modern | I've noticed in datacapture.py, we use a 2x's clock to clock in each half of the data... so maybe that's part of the solution? | 11:29 |
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