| *** tpb has joined #timvideos | 00:00 | |
| *** CarlFK has quit IRC | 01:19 | |
| *** CarlFK has joined #timvideos | 02:02 | |
| *** ChanServ sets mode: +v CarlFK | 02:02 | |
| *** paradisaeidae has joined #timvideos | 02:04 | |
| *** panther has joined #timvideos | 02:13 | |
| panther | Hi | 02:38 |
|---|---|---|
| *** panther is now known as sab_123 | 02:38 | |
| *** paradisaeidae has quit IRC | 02:53 | |
| *** sb0 has joined #timvideos | 03:09 | |
| CarlFK | hi sab_123 | 03:22 |
| sab_123 | hi CarlFK | 03:22 |
| sab_123 | My mentor seems to be rohitksingh | 03:23 |
| sab_123 | I was just wondering how to contact him | 03:23 |
| mithro | Hi sab_123 | 03:37 |
| sab_123 | Hello mithro | 03:37 |
| mithro | sab_123: rohitksingh will be your "primary" mentor, obviously I'll be heavily involved with the project too and it's expected that you'll be talking / interacting with the community quite a bit too | 03:37 |
| sab_123 | mithro, ah okay | 03:38 |
| mithro | CarlFK: back in Chicago yet? | 03:38 |
| sab_123 | mithro, I think Rohit is in the same place that I am located at | 03:38 |
| CarlFK | mithro: not yet. in about 24 hours | 03:38 |
| *** nueces has quit IRC | 03:49 | |
| *** nueces has joined #timvideos | 03:51 | |
| * nueces come back | 03:51 | |
| mithro | hey nueces | 04:21 |
| mithro | I'm just heading out for a bit to grab lunch | 04:21 |
| nueces | the say is stating here in the past, GMT-3 | 04:24 |
| mithro | ? | 04:24 |
| * mithro is UTC+10 | 04:25 | |
| nueces | the day*, sorry | 04:53 |
| nueces | mithro, I send the email, now I going to sleep, I hope the email have some sense :) | 04:54 |
| nueces | is the issue with the non powered hdmi cables fixed? | 04:55 |
| nueces | I build the the firmware and gateware, but not loaded it to the board | 04:56 |
| nueces | just use the serial console to set the settings for the video matrix | 04:58 |
| nueces | but then only get a black image, when previously get the patter video | 04:59 |
| nueces | pattern* | 04:59 |
| *** sab_123 has quit IRC | 05:27 | |
| mithro | nueces: replying to your email now | 05:48 |
| mithro | xfxf: ping? | 06:12 |
| mithro | _florent_: ping? | 06:12 |
| mithro | shenki: So, you going to have any time to work on the UART stuff this weekend? | 06:13 |
| mithro | cr1901_modern: ping? | 06:14 |
| *** sb0 has quit IRC | 06:14 | |
| *** se6astian|away is now known as se6astian | 06:23 | |
| *** tija has joined #timvideos | 06:28 | |
| mithro | Hey tija | 06:32 |
| tija | Hello | 06:32 |
| *** nueces has quit IRC | 07:05 | |
| cr1901_modern | mithro: pong | 09:47 |
| mithro | Did you see we merged the minispartan stuff? | 09:48 |
| cr1901_modern | No I did not, that's great :D! I'll get onto purchasing a small HDMI monitor | 09:48 |
| cr1901_modern | i saw that the issue was closed | 09:48 |
| *** tija has quit IRC | 09:49 | |
| mithro | cr1901_modern: we don't have both input and output working yet. It requires a bunch of fiddling because the FPGA only has 2 PLLs | 09:49 |
| cr1901_modern | Well, you need one PLL for the clock multiplier, one for input clock recovery, and one for output clock recovery | 09:50 |
| cr1901_modern | if worst comes to worst, could you do an ADPLL? | 09:50 |
| cr1901_modern | (there should be a "?" on that preceding sentene) | 09:51 |
| mithro | You only really need on for HDMI in and one for generating the other clocks | 09:53 |
| cr1901_modern | So why does it require so much fiddling then? | 09:54 |
| mithro | But making a single PLL (and some slave DCMs) generate all the clocks for the system, RAM and HDMI out is semi-painful. | 09:55 |
| mithro | Luckily _florent_ has already made the HDMI output accept external clocking. | 09:56 |
| cr1901_modern | mithro: I haven't done that many projects where FPGA resources were at a premium. I'm guessing that needing to route everything via one PLL and BUFG is reducing the system speed? | 09:56 |
| mithro | Nah, it's just figuring out all the multiples and correct values | 09:57 |
| mithro | Probably an afternoons work at most | 09:58 |
| mithro | But still a pain in the butt :-) | 09:59 |
| cr1901_modern | I theorize that any time PLLs are involved, it'll be a pain in the butt :). | 09:59 |
| mithro | I guess you could put it all into the clocking generator that ISE has and the just use the values it outputs. | 10:00 |
| cr1901_modern | For systems with more than 2 PLLs... you simply feed the output of one PLL into the input of another to generate a clock multiple? | 10:01 |
| mithro | Pretty much | 10:02 |
| mithro | The PLLs in the Spartan 6 can generate 5 different output frequencies at once | 10:03 |
| mithro | Be back in 15 minutes | 10:03 |
| cr1901_modern | Ahhh, (I kinda glazed over the parameters in MiSoC :P) | 10:03 |
| *** se6astian is now known as se6astian|away | 10:17 | |
| *** Bertl_zZ is now known as Bertl | 10:18 | |
| cr1901_modern | mithro: Do you have a timetable for going to the new MiSoC API? | 11:01 |
| mithro | back now | 11:16 |
| mithro | cr1901_modern: next month or so I think | 11:16 |
| mithro | _florent_ would know how far along he is :) | 11:16 |
| *** se6astian|away is now known as se6astian | 11:24 | |
| cr1901_modern | mithro: Looking forward to it! Building SoC's w/ MiSoC has gotten a lot easier since then :D | 11:43 |
| *** se6astian is now known as se6astian|away | 12:18 | |
| *** se6astian|away is now known as se6astian | 12:21 | |
| *** sb0 has joined #timvideos | 15:26 | |
| *** CarlFK has quit IRC | 15:45 | |
| *** sb0 has quit IRC | 15:51 | |
| *** Bertl is now known as Bertl_zZ | 17:36 | |
| *** Bertl_zZ is now known as Bertl | 19:13 | |
| *** se6astian is now known as se6astian|away | 21:29 | |
| *** CarlFK has joined #timvideos | 23:16 | |
| *** ChanServ sets mode: +v CarlFK | 23:16 | |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!