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| mithro | shenki: ping? | 05:17 |
|---|---|---|
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| shenki | mithro: pong | 05:24 |
| mithro | shenki: how are things? I'm guessing you've been pretty busy as I haven't seen you around here much | 05:24 |
| mithro | CarlFK: ping? | 05:27 |
| CarlFK | mithro: pong | 05:27 |
| mithro | CarlFK: I sent you some instructions in reply to your email. Do they make sense? | 05:27 |
| shenki | mithro: yeah. I'm in Canberra for the second time this month, this time for 10 days | 05:31 |
| mithro | shenki: well, if you ever want to pop down to Sydney, you are always welcome to crash on my couch (assuming nobody else is using it :) | 05:33 |
| shenki | mithro: thanks :) I considered trying to make it part of the trip, but i didn't work out this tim | 05:34 |
| shenki | this time | 05:34 |
| shenki | mithro: next trip i'll make sure i come over for a day or two | 05:35 |
| shenki | mithro: what's new with you? | 05:35 |
| mithro | shenki: if you wanted to take a day off on a Monday or Friday, I would love to take one off too | 05:35 |
| mithro | shenki: personal wise, not much | 05:36 |
| mithro | shenki: project wise - been playing with misoc/migen from the #m-labs guys, getting very close to sending the rev2 board off for prototyping | 05:36 |
| shenki | very cool | 05:37 |
| shenki | mithro: what have you got migen doing? | 05:37 |
| mithro | the main reason I'm interested in the misoc/migen stuff is they have a bunch of fully open cores for things like DDR, Ethernet, PCI-Express which works across a wide variety of FPGAs | 05:39 |
| mithro | IE Spartan 6, Atrix (such as in the Zynq), etc | 05:40 |
| shenki | cool. so it makes us less dependant on the IDEs and IP provided by the vendors | 05:44 |
| mithro | shenki: yes | 05:44 |
| shenki | easier to run the same firmware across multiple famlies | 05:44 |
| shenki | famililes | 05:44 |
| shenki | families | 05:44 |
| mithro | Yeah | 05:44 |
| mithro | if we want to support Zynq and Novena, misoc seems like a good option | 05:45 |
| mithro | Couple of downsides | 05:45 |
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| mithro | Set up is a lot harder than just install the Xilinx tools, it requires a custom compiled gcc+binutils because they do the RAM initialisation using a CPU softcore | 05:46 |
| mithro | Most of their cores is written in migen, which has a much smaller user base then vhdl / verilog | 05:47 |
| mithro | But migen is much nicer than raw vhdl / verilog in many ways - not as nice as cfelton's myhdl | 05:48 |
| mithro | The only missing parts in misoc which we need for a HDMI2USB are our custom USB stuff and a mjpeg core | 05:48 |
| shenki | you can still integrate with vhdl cores? | 05:48 |
| mithro | shenki: yes | 05:48 |
| CarlFK | mithro: instructions - I think so. | 05:49 |
| mithro | CarlFK: please attach anything you managed to collect to that bug | 05:49 |
| CarlFK | mithro: is the i2c timing controlled by the fpga code (or whatever it is called) something we control, or is it built into the atlys board? | 05:50 |
| mithro | shenki: Carl's email about https://github.com/timvideos/HDMI2USB/issues/105 reminded me that I've been meaning to catch up with you :) | 05:50 |
| tpb | Title: Debug unreliable screen detection and possible EDID issue · Issue #105 · timvideos/HDMI2USB · GitHub (at github.com) | 05:50 |
| mithro | CarlFK: IIRC the laptop controls the clock for the EDID I2C | 05:51 |
| shenki | mithro: yeah. i'd like to find some time to spend on that | 05:51 |
| mithro | shenki: yeah - I should spend some time looking into it too | 05:51 |
| CarlFK | mithro: but does the fpga lookto the i2c clock and form the data bit signal? (which seems the only way this would be broken) | 05:53 |
| CarlFK | I would expect the i2c protocol to be implemented in support chips. but yeah, I don't really know what I am talking about :p | 05:54 |
| mithro | I think shenki knows the details about the i2c stuff better than myself | 05:55 |
| mithro | The basic idea is that the laptop will send some commands to the FPGA saying "please send me the EDID data" which the FPGA then response too. | 05:55 |
| mithro | The FPGA is basically pretending to be an EEPROM memory device. | 05:55 |
| mithro | So there could be a bunch of things going wrong | 05:57 |
| CarlFK | I was told "sound like the i2c communication isn't done right. a scope might show that." which surprised me | 05:57 |
| mithro | The scope will give you the "raw data" for what is being sent / received. | 05:57 |
| mithro | Which you can then decode into the I2C commands / responses. | 05:58 |
| CarlFK | "the bits might not be aligned with the clock, or they may not be square enough, they could rise from 0 to 1 in a slope that is out of spec." | 05:59 |
| shenki | we captured that, in the failure case, and it appeared to be fine | 05:59 |
| mithro | shenki: I don't think we trust our capture device in that case, right? | 05:59 |
| CarlFK | ah. yeah. I suspect this is from historic problems building i2c from scratch, not build into a board like the atlys. | 05:59 |
| shenki | mithro: yeah. not enough to write it off, but it is evidence that the hypothesis is wrong | 06:00 |
| CarlFK | but don't worry, Ill go down this path- it's easy enough for me. | 06:00 |
| shenki | i suspect it's due to a lack of integrity in the presence signal | 06:00 |
| shenki | so the device keeps on re-appearing to the host | 06:00 |
| mithro | CarlFK: those are all low level things which could cause the I2C signal to be wrong | 06:00 |
| shenki | that issue is compounded by our all of testing being through HDMI/DVI -> DP | 06:01 |
| shenki | so we introduce someone else's chipset to the mix | 06:01 |
| mithro | shenki: each time a "reappearing" occurs there should be a new set of I2C communication, right? | 06:01 |
| mithro | CarlFK: if the signal timing / levels / etc are wrong then the data is probably not getting through correctly | 06:02 |
| CarlFK | mithro: sounds like things that would have been designed and implemented by Digilent Atlys devs and manufacturing, not the fpga code. | 06:02 |
| mithro | CarlFK: no, that is the point of an FPGA - this is done in software now instead of hardware | 06:02 |
| CarlFK | k, that's what I wasn't sure of | 06:03 |
| mithro | CarlFK: otherwise we couldn't customise it | 06:03 |
| shenki | mithro: right. but that could be all kinds of confusing to any of the systems in chain - FPGA, adapter, PC - if we're strobing the connection line | 06:03 |
| mithro | shenki: we don't actually have control over the HPD line on the Atlys board, it is hard wired | 06:04 |
| shenki | mithro: yeah | 06:04 |
| mithro | CarlFK: btw can you describe the unreliable setup you have? | 06:04 |
| shenki | mithro: we can still scope it, see what the signal integrity looks like | 06:04 |
| mithro | shenki: yeah | 06:04 |
| mithro | shenki: much harder to scope though :( | 06:04 |
| shenki | yeah | 06:04 |
| mithro | CarlFK: does your scope friend have a github account? | 06:05 |
| CarlFK | my "LENOVO ThinkPad Twist 33474HU" laptop (that I do all my dev on) has a display port and a mini hdmi. DP -> htmi dongle ->atlys works fine. | 06:07 |
| CarlFK | mini hdmi -> atlys, about 50% of the time xrandr shows the correct res | 06:07 |
| CarlFK | watch xrandr shows it fliping between good and not good values, including xrandr segfaulting | 06:08 |
| CarlFK | I haven't been able to capture not good | 06:08 |
| CarlFK | also, even when not runing xrandr over and over, after the first one, I see syslog detecting a new hdmi device every second or two. but that may just be ubuntu hot plug going wonky. | 06:10 |
| CarlFK | and my cpu load goes nuts and things get very unresponsive, which makes it hard to gather stats | 06:11 |
| CarlFK | mithro: scope guy is a ps1 member that I don't really know. someone else knows he generally brings it to the SOC meetings every two weeks | 06:14 |
| mithro | CarlFK: on a related note, one thing which would be useful to research EDID information and decode what is actually in our EDID hex blocks | 06:14 |
| mithro | CarlFK: our EDID block might be technically valid but actually unusual in some way which Linux doesn't like | 06:15 |
| CarlFK | good news: this scope has a bunch of protocol decoders, so it should be able to dump that in human readable or maybe even to a usb stick or something wonderful | 06:16 |
| mithro | CarlFK: please try and get the raw trace values too | 06:18 |
| mithro | CarlFK: but most scopes have a way to dump that data to something like a CSV or similar file | 06:18 |
| CarlFK | mithro: the NERP meeting starts at 7, I expect 8:30 will be when it breaks and Andrew will start probing the i2c stuff. I'll ping you here on IRC. I expect he will know what sorts of things will be useful | 06:24 |
| mithro | okay | 06:24 |
| mithro | when is this? | 06:25 |
| CarlFK | in about 18 hours | 06:29 |
| mithro | okay | 06:30 |
| CarlFK | 20:30 - 1:30 now = 19 hours | 06:30 |
| CarlFK | that. | 06:30 |
| mithro | CarlFK: okay, I'll try and be around - but don't know if I will | 06:41 |
| CarlFK | understood | 06:42 |
| CarlFK | I suspect in 2 weeks I'll have a hdmi break out and do another ... scoping | 06:56 |
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| MaZderMind | so, back from a sunny weekend. | 08:13 |
| MaZderMind | CarlFK: "if you needed to record something next week, would you use dvswitch" - it depends. For a conference and if they don't have hardware mixers present: yes. For Single-Talks we're experimenting with recording slides and cam in parallel and mix them during the final encoding : | 08:15 |
| MaZderMind | CarlFK: "if you needed to record something next week, would you use dvswitch" - it depends. For a conference and if they don't have hardware mixers present: yes. For Single-Talks we're experimenting with recording slides and cam in parallel and mix them during the final encoding: http://c3voc.mazdermind.de/50-hd-mix.mp4 | 08:15 |
| MaZderMind | CarlFK: mithro did you try the Epiphan EDID-Files? They have a collection of various EDID-Blobs to use: | 08:23 |
| MaZderMind | http://www.epiphan.com/products/dvi2usb-3-0/downloads/ | 08:23 |
| tpb | Title: DVI2USB 3.0 downloads (at www.epiphan.com) | 08:23 |
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| MaZderMind | used the weekend to get into vhdl: https://twitter.com/mazdermind/status/592375853163515904 https://twitter.com/mazdermind/status/592269536189149184 https://twitter.com/mazdermind/status/592269875818659840 https://twitter.com/mazdermind/status/592378775104434176 | 10:50 |
| tpb | Title: mazdermind on Twitter: "When I look at it, my bench looks nearly as crowded as @eevblogs. time to hire… no. to clean up. http://t.co/Shxb1MzasW" (at twitter.com) | 10:50 |
| MaZderMind | slowly getting used to it | 10:50 |
| mithro | MaZderMind: if you wanted to take a look at https://github.com/timvideos/HDMI2USB/issues/105 too, it can't hurt to have more traces. | 10:51 |
| tpb | Title: Debug unreliable screen detection and possible EDID issue · Issue #105 · timvideos/HDMI2USB · GitHub (at github.com) | 10:52 |
| mithro | MaZderMind: At the moment changing the edid hex files requires recompiling the firmware | 10:52 |
| mithro | MaZderMind: I realise now that we should have some way to dynamically load the EDID data | 10:52 |
| mithro | MaZderMind: there are instructions on the issue about what / where to capture stuff | 10:57 |
| MaZderMind | mithro: i'll take a look at it when I'm ready to | 10:57 |
| MaZderMind | still learning fpgs-basics, I want to build my own view on how things work instead of just probing & guessing around | 10:58 |
| mithro | MaZderMind: no worries | 11:02 |
| mithro | MaZderMind: if you have questions, please do feel free to ask here - even if it's just general FPGA questions | 11:02 |
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| CarlFK | MaZderMind: my point is you wouldn't use gst-switch | 13:21 |
| MaZderMind | CarlFK: no, because there are some unsolved problems that makes it unusable in our setup: | 13:30 |
| MaZderMind | https://github.com/timvideos/gst-switch/issues/111 for example | 13:31 |
| tpb | Title: GUI<->Server via GBit Ethernet · Issue #111 · timvideos/gst-switch · GitHub (at github.com) | 13:31 |
| MaZderMind | CarlFK: but I hope to get the blockers solved over the year and to have gst-switch as viable solution for autumn and the coming year | 13:31 |
| MaZderMind | CarlFK: we have a whole lot of conference to play at: https://c3voc.de/wiki/#section2015 | 13:32 |
| tpb | Title: Start [CCC VOC] (at c3voc.de) | 13:32 |
| CarlFK | MaZderMind: I think this should be one of the easier fpga tasks https://github.com/timvideos/HDMI2USB/issues/102 | 13:40 |
| tpb | Title: Map 720p and 1024x768 to a hardware switch · Issue #102 · timvideos/HDMI2USB · GitHub (at github.com) | 13:40 |
| CarlFK | MaZderMind: I think timvideos/gst-switch can be used sooner. | 13:53 |
| CarlFK | it just needs to function like dvswtich v.6 or whatever version they first used. no pnp, no fade, just switch between streams | 13:54 |
| mithro | CarlFK: have you tried that recently? | 13:57 |
| CarlFK | just ran it. I don't see anything new | 14:00 |
| mithro | CarlFK: what is missing from switching between streams in that UI? | 14:04 |
| MaZderMind | the blocker for the VOC testing gst-switch in production are the #102 (srv <-> ui via ethernet) and that possible memleak | 14:07 |
| MaZderMind | but I planned on doing it right: fix the tests, rewrite the GUI and *then* work on the missing server parts | 14:07 |
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| CarlFK | sorry folks - ran it with 2 test streams and my CPU meeter pegged then froze and I had to power cycle | 14:14 |
| mithro | I need to head home | 14:19 |
| mithro | gnight | 14:19 |
| MaZderMind | night mithro | 14:21 |
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| skay | mithro: Carl is rebooting | 14:23 |
| skay | I'm busy | 14:23 |
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| CarlFK1 | ok, no more running anything but irc | 14:24 |
| CarlFK1 | last time I tried to do some testing, I realized I couldn't figure out how to operate it | 14:25 |
| CarlFK1 | I ended up with a 2nd laptop with docs open in a window | 14:26 |
| CarlFK1 | and bouncing between the docs and the UI for a few min didn't seem to be training my memory | 14:26 |
| CarlFK1 | mithro: did I loose you? | 14:30 |
| cfelton | CarlFK1: yes, I believe mithro left | 14:33 |
| CarlFK1 | thanks | 14:34 |
| CarlFK1 | MaZderMind: can you clone and run https://github.com/CarlFK/dvsmon/blob/master/mixy.sh | 14:40 |
| tpb | Title: dvsmon/mixy.sh at master · CarlFK/dvsmon · GitHub (at github.com) | 14:40 |
| CarlFK1 | either clone it in the right place or change PATH="`pwd`/../gst-switch/tools:$PATH" | 14:41 |
| CarlFK1 | brb | 14:41 |
| MaZderMind | CarlFK1: seems an -f is required on the server (my defaults may be different) | 14:49 |
| MaZderMind | despite that it runs quite nicely | 14:49 |
| CarlFK1 | ah right. what's the -f I need to work with my test streams ? | 15:01 |
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| MaZderMind | CarlFK1: well it just needs to be the same for sources & server, see https://github.com/timvideos/gst-switch/blob/master/run-demo.sh | 15:18 |
| tpb | Title: gst-switch/run-demo.sh at master · timvideos/gst-switch · GitHub (at github.com) | 15:18 |
| CarlFK1 | oh neat I didn't realize it would take gstreamer .. um.. thingy ;) | 15:19 |
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| CarlFK | AUDIO_CAPS="audio/x-raw, rate=48000, channels=2, format=S16LE, layout=interleaved" | 17:28 |
| CarlFK | audio ... interleaved ? | 17:29 |
| CarlFK | MaZderMind: you mind checking the changes to mixy.py I just pushed - I copied the params from run-demo.sh and fumbled a bit with getting python string stuff to play nice. | 18:40 |
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| MaZderMind | interleaved should be sth like joint stereo | 21:47 |
| MaZderMind | i'll check tomorrow, that vhdl stuff is currently more interesting | 21:48 |
| CarlFK | ah, right. as long as it might be valid, that's good enough | 22:08 |
| CarlFK | did you see my comment about implementing the 1024 / 1280 switch? | 22:08 |
| CarlFK | even just flipping the current build back to 720p would be nice | 22:09 |
| CarlFK | bbl | 22:09 |
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