| *** tpb has joined #timvideos | 00:00 | |
| *** hait has quit IRC | 00:27 | |
| *** Niharika_ has joined #timvideos | 02:45 | |
| mithro | I'm still alive! | 03:27 |
|---|---|---|
| techman83 | w00 | 03:27 |
| mithro | shenki: ping? | 03:30 |
| mithro | MaZderMind: ping? | 03:30 |
| mithro | techman83: are you going to have time to be a mentor again this year? | 03:34 |
| shenki | mithro: hello | 03:40 |
| mithro | shenki: how are things? | 03:41 |
| shenki | mithro: not too bad. how are you? | 03:42 |
| mithro | I get to eat puree food now | 03:42 |
| techman83 | mithro, should do | 03:43 |
| techman83 | mithro, not moving office again :P | 03:43 |
| mithro | techman83: aren't you unemployed? | 03:44 |
| techman83 | mithro, Nah. I'm still employed. | 03:45 |
| techman83 | mithro, though I could be technically could be moving myself to a new office at some point :P - but that should be considerably less effort | 03:47 |
| mithro | okay | 03:49 |
| techman83 | xfxf might be though, pending if he found something yet | 03:50 |
| shenki | mithro: \o/ | 04:08 |
| shenki | mithro: are you back at work? | 04:08 |
| mithro | shenki: nah, decided to take the week off | 04:08 |
| mithro | techman83: do you have those photos from the hackfest | 04:08 |
| techman83 | mithro: I have to upload them somewhere. I didn't get a lot. But there are a couple of good shots. | 04:09 |
| mithro | techman83: can you do that ASAP | 04:09 |
| techman83 | Let me do that now, then I can mark that off my todo list | 04:09 |
| *** CarlFK has joined #timvideos | 04:12 | |
| *** ChanServ sets mode: +v CarlFK | 04:12 | |
| techman83 | mithro: https://plus.google.com/photos/106636702849949888554/albums/6116660961546516945 | 04:13 |
| techman83 | mithro, sorry I didn't get more | 04:13 |
| mithro | techman83: if you want to procrastiant from doing real work, I could use some help actually writing a blog post to go with the photos | 04:14 |
| *** sharebrained has left #timvideos | 04:14 | |
| techman83 | mithro, I've a bit of a backlog of day to day stuff - but if you start a doc somewhere with some paragraph headings I can probably contribute | 04:15 |
| techman83 | oh that's right, G+ killed my shortname because it wasn't my real name | 04:17 |
| techman83 | (was noting why it was numbers) | 04:17 |
| techman83 | I recall being rather annoyed at some point :P | 04:17 |
| mithro | sounds like google plus | 04:27 |
| *** revsi has joined #timvideos | 04:30 | |
| mithro | shenki: any luck with looking at the edid stuff? | 04:33 |
| shenki | mithro: not yet. perhaps tomorrow night i;ll have some time | 04:33 |
| aps | shenki: busy with the WC? :P | 04:48 |
| mithro | http://ʘ‿ʘ.tk/ | 05:04 |
| mithro | http://✉.tk/ | 05:05 |
| shenki | aps: it's been great! | 05:16 |
| shenki | aps: i went to the india v pakistan game | 05:16 |
| shenki | aps: i thought i'd been teleported to india. the entire ground was full of indian people! | 05:16 |
| *** tija has joined #timvideos | 05:27 | |
| mithro | shenki: I saw something about 5x more people from India / Pakistan visit for the WC than for the total of the rest of the year | 05:28 |
| mithro | hey tija | 05:28 |
| tija | hi mithro! | 05:29 |
| shenki | mithro: yeah, the place was overrun. they kept the airport open overnight so people had somewhere to stay, as all the hotels were full | 05:42 |
| tija | mithro: A friend of mine wanted to know the image processing project part of speaker track is done or not? | 05:44 |
| mithro | tija: kinda | 05:44 |
| tija | what parts are left? | 05:44 |
| mithro | tija: the big part is getting the PTZ controller stuff into gstreamer | 06:00 |
| mithro | and getting everything working again | 06:03 |
| mithro | techman83: take a look at that doc again? | 06:07 |
| techman83 | mithro, looking now | 06:08 |
| shenki | tija: so what needs to be done to port hdmi2usb to the zybo? | 06:09 |
| tija | The architecture of spartan6 and zynq is different. The DDR in sparatan is connected to fpga (ofcourse) but in zynq is connected to PS. | 06:10 |
| tija | So we need a VDMA to send data from PL to PS. Also As zynq is a system on chip, major blocks of firmware need a AXI interface. | 06:11 |
| tija | Also a vga module is required as zybo doesn't have two hdmi ports | 06:16 |
| *** sirnam has joined #timvideos | 06:23 | |
| mithro | http://ramtin-amin.fr/#tristar | 07:10 |
| tpb | Title: Ramtin Amin Web Blog (at ramtin-amin.fr) | 07:10 |
| mithro | tija: for a zybo port, you probably only need to worry about getting the HDMI data onto an AXI bus which the ARM chip can then read | 07:11 |
| tija | mithro: do you want compression in PS? | 07:12 |
| mithro | tija: I'd ignore that for now | 07:12 |
| tija | mithro: What you are saying is right. As the HDMI produces data continuously, we need a axi stream interface, then we need a axi VDMA which transfers data form PS to PL. | 07:16 |
| tija | http://www.xilinx.com/support/documentation/application_notes/xapp792-high-performance-video-zynq.pdf | 07:16 |
| tija | But then we need to bring back data into PL for compression, so we need another dma | 07:17 |
| mithro | tija: it would be worth seeing if the ARM core can do compress | 07:17 |
| tija | mithro: I checked that. I think it is difficult. | 07:20 |
| tija | http://smorgasbork.com/component/content/article/97-real-time-mpeg-2-encoding-with-ffmpeg | 07:20 |
| tpb | Title: Real-time MPEG-2 encoding with ffmpeg (at smorgasbork.com) | 07:20 |
| tija | http://smorgasbork.com/component/content/article/35-linux/98-high-bitrate-real-time-mpeg-2-encoding-with-ffmpeg | 07:21 |
| tpb | Title: High bitrate real-time MPEG-2 encoding with ffmpeg (at smorgasbork.com) | 07:21 |
| mithro | tija: we have a 1Gigabit ethernet interface to get the data out, so we don't need much compression | 07:22 |
| mithro | tija: does the ARM hard core have any hard accelerators in it too? (Say in the GPU?) | 07:23 |
| tija | mithro: In case we are using ethernet then we don't need to compress for 720p. Atleast this is what Tariq proposed. | 07:24 |
| mithro | tija: possibly | 07:24 |
| mithro | the Zybo doesn't have SATA right? | 07:24 |
| tija | no it doesn't | 07:25 |
| mithro | tija: I'd work on trying to get a screenshot out of the HDMI input first | 07:25 |
| mithro | the SERDES in the Zybo are slightly different to the Spartan 6 SERDES | 07:27 |
| tija | mithro: That is easy if you don't want all open source stuff. http://xillybus.com/ | 07:27 |
| tpb | Title: An FPGA IP core for easy DMA over PCIe with Windows and Linux | xillybus.com (at xillybus.com) | 07:27 |
| mithro | tija: you just said "That easy if we don't do what we want to do" | 07:27 |
| mithro | :P | 07:27 |
| tija | They give us a fifo like interface and on arm side their driver allows reading from a file just like a tty* thing. | 07:29 |
| mithro | tija: we want the FPGA core to be FOSS | 07:29 |
| tija | Their drivers are open source. It would be great if someone can reverse engineer the driver to create a FOSS ip core for the drivers. | 07:30 |
| tija | This would ease the use of zynq chips. | 07:30 |
| mithro | it would be nice if the interface on the ARM side was just a V4L device | 07:31 |
| tija | V4L supports only USB? | 07:32 |
| mithro | no | 07:33 |
| mithro | v4l is a kernel to userspace interface | 07:33 |
| *** revsi has left #timvideos | 07:33 | |
| tija | Anyways I can get HDMI screenshot with some hardwork but I will have to use free IPs of Xilinx. | 07:35 |
| tija | Creating a VDMA core that works is really tough. | 07:36 |
| mithro | take a look at the misoc / migen stuff from #m-labs | 07:38 |
| *** Niharika_ has quit IRC | 07:40 | |
| *** Niharika_ has joined #timvideos | 07:51 | |
| *** Niharika_ has quit IRC | 09:40 | |
| *** sirnam has quit IRC | 11:10 | |
| *** sirnam has joined #timvideos | 11:22 | |
| shenki | tija: i watched this presentation the other day, about making fpgas easier to use | 12:13 |
| shenki | tija: you might find the ideas interesting | 12:13 |
| shenki | tija: https://www.youtube.com/watch?v=8-OR0QppWKA | 12:13 |
| tpb | Title: Towards General Purpose Reconfigurable Computing on Novena - FPGAs for Everybody with Novena [31c3] - YouTube (at www.youtube.com) | 12:13 |
| MaZderMind | mithro: pong… somehow | 12:17 |
| MaZderMind | I'm still working on getting the new integration tests pass every time. currently they fail with a 2% probability false-positive | 12:31 |
| MaZderMind | I have an idea what's up but only some minutes a day to work on | 12:32 |
| MaZderMind | in KW11 we have an open yource geo conference we'll be recording, more gst-switch experiments there :) | 12:32 |
| mithro | MaZderMind: okay - I'm around again now | 12:36 |
| tija | shenki: I posted the same link on irc two days ago. :D | 12:37 |
| mithro | tija: it would be nice if the work you did for the Zybo meant that shenki could do his HDMI2Novena module too | 12:37 |
| mithro | tija: I don't think we'd do a gst-switch + speaker tracking in this years GSoC | 12:41 |
| mithro | tija: we want to concentrate on making gst-switch awesome and super stable for the switching case | 12:42 |
| mithro | MaZderMind: have you got a push of your new integration tests somewere? | 12:42 |
| mithro | MaZderMind: I'll take a look and see if I can track down stuff tomorrow | 12:42 |
| tija | mithro: I am don't know the novena architecture well but since it has a spartan6 lx45 with a DDR2 attached to it, porting will be easier. Instead of spitting data out of USB we have to bring it into novena processor. | 12:45 |
| tija | In zybo it is a bit differenct because of DDR attached to PS not PL. | 12:46 |
| mithro | tija: the interface between the Novena is an AXI like from what I understand | 12:46 |
| mithro | tija: which is similar how the PS and PL talk in the Zybo | 12:46 |
| tija | mithro: In that case porting to zybo should help. | 12:47 |
| mithro | I think shenki knows more | 12:48 |
| mithro | shenki: I forgot to send some of the adapters back with my parents | 12:48 |
| MaZderMind | mithro: it's a branch in my repo | 12:49 |
| MaZderMind | just found the pretty old pexpect modukle which does essetially what I'm doing too but is probably better tested and already past the thrweading/blocking issues my code has ^^ | 12:49 |
| MaZderMind | I wanted to give it a try today | 12:50 |
| *** Nooob has joined #timvideos | 12:50 | |
| mithro | okay | 12:51 |
| mithro | I should probably go to bed soonish | 12:51 |
| mithro | MaZderMind: still need to finish the moving files around | 12:51 |
| mithro | s/still/I still/ | 12:51 |
| MaZderMind | have to do urgent paid work anyway now ;) | 12:51 |
| MaZderMind | mithro: yes, that would probably a good thing to finish first | 12:52 |
| MaZderMind | while I'm still playing with the int-tests. | 12:52 |
| MaZderMind | I can't really give promises atm. but if my pexpect-plans work out I might have the rewritten int-tests ready around upcoming sunday | 12:53 |
| *** f15h has joined #timvideos | 12:59 | |
| *** f15h has quit IRC | 13:03 | |
| *** Niharika has joined #timvideos | 13:14 | |
| cfelton | mithro/shenki/tija: why the port to the zybo? (curious not questioning if)' | 14:03 |
| cfelton | to utilize the PS? | 14:05 |
| tija | cfelton: Zybo | 14:52 |
| tija | cfelton: Zybo's PS can run a full fleged linux system. As linux has a well developed TCP/IP stack, we can make use of that. Also, porting to zybo will help us port our firmware to Novena which has a similar FPGA/Processor architecture. | 14:53 |
| cfelton | tija: understand, so the answer is to use the PS. | 14:55 |
| tija | cfelton: Ha! yes to use PS | 14:55 |
| cfelton | tija: from the above conversation it is speculative that the port will help Novena, true? | 14:55 |
| *** sirnam has quit IRC | 14:57 | |
| tija | cfelton: I am not well aware of novena architecture. I feel it will be easier to port to novena as it has a spartan 6. All we have to do is send data via axi stream interface to processor and write drivers to capture the incoming data. | 14:59 |
| cfelton | tija: fun stuff, why the Zybo vs. parallela, Zed, etc. | 14:59 |
| tija | cfelton: Zybo is the cheapest of all. | 14:59 |
| tija | parallela does not have an input hdmi/vga | 15:00 |
| tija | zed is pretty expensive. | 15:00 |
| cfelton | tija: ahh yes, thanks | 15:01 |
| *** udara28 has joined #timvideos | 15:01 | |
| udara28 | Hi! I'm udara a student from Univerisyt of Moratuwa, Sri Lanka | 15:05 |
| MaZderMind | The Zybo is in a Price-Range (~170€) which I would pay to just try out working with your stuff, while the Atlys is a little off (~440€) | 15:05 |
| udara28 | is timvideos applying as a mentor organization for GSOC 2015? | 15:06 |
| CarlFK | udara28: yes | 15:07 |
| udara28 | CarlFK: thanks :) and looking foward for applying | 15:08 |
| cfelton | MaZderMind: definitely, yeah the Atlys is a spendy board. | 15:17 |
| cfelton | anyone have a Zybo yet? | 15:18 |
| cfelton | MaZderMind/tija: when ordering a Zybo do you need to get the Vivado voucher? | 15:18 |
| cfelton | moving to Vivado won't be so fun - ugh | 15:19 |
| tija | cfelton: mithro "loaned" me and rohit a zybo. It did not have a Vivado voucher. They give a 1 month trial which I extend every month. | 15:19 |
| cfelton | fun | 15:20 |
| tija | cfelton: Yes moving to vivado is pain. but the block design feature and HLS is awesome. | 15:20 |
| MaZderMind | Hum I have not done anything with fpgas yet. is this vivado a requirement? a voucher would be +20€ only, though | 15:22 |
| cfelton | tija: I don't think the Vivado HLS is that great, I have written about it a couple times. Haven't seen the block design, typically these only seem useful for "toy" examples. Once you have a large complex system that you want to have many "personalities" the block design sofware fall apart quick (my POV). Take that with a grain of salt, I haven't used the | 15:24 |
| cfelton | Vivado block thingy | 15:24 |
| cfelton | Yes, Vivado is required for Zynq devices | 15:24 |
| cfelton | The voucher seems worth it to avoid the pain of constantly renewing | 15:24 |
| cfelton | hopefully the voucher isn't tied to a specific Vivado version (?) | 15:25 |
| tija | cfelton: A company working on FPGA where I interned used HLS to port an open source TCP/IP stack to FPGA. The advantage with HLS is that long verification time is avoided. Ofcourse it is still not possible achieve performance of hand written verilog or vhdl. | 15:27 |
| cfelton | tija: why is the verification avoided? | 15:29 |
| tija | cfelton: HLS are bit accurate (atleast the companies claim it to be), so you can write a C code and it's test bench in C and it is good enough to verify you created block. No system verilog is required. | 15:31 |
| cfelton | tija: my take, is that you still need to think in a highly-parallel structure. Typically this means a different implementation. Once you work through the appropriate design the imperative C with pragmas buys little (from my experience watching designers trying to use it). | 15:31 |
| cfelton | tija: many do not do verification in V* Doing verification in C is a negative from my point of view :) | 15:32 |
| cfelton | I do agree, no SV for verification is a good thing | 15:33 |
| tija | cfelton: Yes that is true. I can't take a normal C code and get good performance on FPGA using HLS. | 15:33 |
| cfelton | tija: my take, is once you structure the approach correctly (what is the best design for the task) the benefits of a C base HLS shrink quickly. | 15:34 |
| cfelton | tija: no disclaimers, my take from my experiences. | 15:35 |
| tija | cfelton: There is other side to it. If you need a core which changes a lot, using rtl is expensive. A small change will require to long cycle of design and verification. Not true if HLS is being used. | 15:37 |
| *** sirnam has joined #timvideos | 16:09 | |
| cfelton | tija: I am not sure if I buy that. It might be true depending on the design groups experience etc. | 16:20 |
| cfelton | tija: I am sure there are uses but I haven't come across any good examples yet :) | 16:21 |
| cfelton | tija: if you have an example, I would be very interested. Typically I haven't found much benefit http://www.fpgarelated.com/showarticle/578.php | 16:23 |
| tpb | Title: Little to no benefit from C based HLS (at www.fpgarelated.com) | 16:23 |
| tija | Honestly I don't have an example as my industry experience is negligible. What I am saying is out of my experience as intern. I am biased towards HLS because it is my research topic at university. | 16:35 |
| cfelton | tija: it has been a hot research topic for many-many moons. I am not trying to discourage, I think it is one of those things that looks more promising than it is and there is a plethora of anecdotal examples that keep our hopes alive :) | 16:50 |
| cfelton | tija: I looked quickly at the novena FPGA to CPU interface and it isn't an AXI-Stream (as far as I understand AXI-stream). It is a memory-mapped interface (data and address) and I would guess with DMA like transfers for bulk data. I didn't see any throughput numbers though. | 16:59 |
| tija | cfelton: link? | 17:03 |
| cfelton | tija: it is referred to as EIM interface | 17:03 |
| cfelton | from the IRC channel and github https://github.com/bunnie/novena-gpbb-fpga/blob/master/novena-gpbb.srcs/sources_1/imports/imports/novena_fpga.v | 17:03 |
| tpb | Title: novena-gpbb-fpga/novena_fpga.v at master · bunnie/novena-gpbb-fpga · GitHub (at github.com) | 17:03 |
| tija | cfelton: Novena has a EIM register interface which as you said is a memory mapped interface. And the drivers for the same are already present. So now the bottle neck is sending in HDMI input to fpga. | 17:21 |
| tija | https://github.com/bunnie/novena-fpga-drivers/blob/master/eim.c | 17:21 |
| tpb | Title: novena-fpga-drivers/eim.c at master · bunnie/novena-fpga-drivers · GitHub (at github.com) | 17:21 |
| tija | "Spartan-6 CSG324-packaged FPGA (PVT uses LX45: 43k logic cells, 6.8k slices, 54.5k ff, 401kb distributed RAM, 58 DSP48A, 2088kb block RAM) — has several interfaces to the CPU, including a 2Gbit/s (peak) RAM-like bus — for your bitcoin mining needs. Or whatever else you might want to toss in an FPGA." | 17:22 |
| tija | http://www.kosagi.com/w/index.php?title=Novena_Main_Page#Hardware_Design_Source | 17:23 |
| tpb | Title: Novena Main Page - Studio Kousagi Wiki (at www.kosagi.com) | 17:23 |
| cfelton | tija: I didn't understand your bottleneck comment? | 17:28 |
| tija | cfelton: We have to create an expansion board so that we can send HDMI signal to FPGA. Otherwise it is easy to port our firmware to novena. | 17:30 |
| cfelton | tija: ic, the expansion interface is slower than the EIM? | 17:31 |
| tija | cfelton: I am not sure. How does that matter? | 17:32 |
| cfelton | tija: I don't think it does, I was trying to relate it back to your comment and understand the context. Maybe you meant bottleneck as in development and not device performance | 17:39 |
| tija | cfelton: yes development! | 17:40 |
| *** udara28 has left #timvideos | 17:51 | |
| *** slomo has quit IRC | 18:31 | |
| *** CarlFK has quit IRC | 18:40 | |
| *** Nooob has quit IRC | 19:24 | |
| *** CarlFK has joined #timvideos | 19:31 | |
| *** ChanServ sets mode: +v CarlFK | 19:31 | |
| *** sirnam has quit IRC | 19:34 | |
| *** Niharika has quit IRC | 19:51 | |
| *** tija has quit IRC | 20:14 | |
| *** CarlFK has quit IRC | 21:35 | |
| *** CarlFK has joined #timvideos | 21:37 | |
| *** ChanServ sets mode: +v CarlFK | 21:37 | |
| mithro | tija: we have a year licence for vivado | 21:41 |
| *** CarlFK has quit IRC | 23:06 | |
| mithro | The Atlys board has been discontinued :( | 23:15 |
| mithro | Guess I better hurry up with the prod board | 23:15 |
Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!