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| abhinav95 | Hi | 08:13 |
|---|---|---|
| abhinav95 | Can I get some details about project HDMI2USB#15 ? PDF uploaded on the link "http://www.usb.org/developers/devclass_docs/audio10.pdf" is not getting opened up and reporting "resource not found". | 08:13 |
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| tija | abhinav95: http://www.usb.org/developers/docs/devclass_docs/audio10.pdf | 13:49 |
| tija | this works for me | 13:49 |
| abhinav95 | tija: Thanks. | 14:04 |
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| CarlFK | https://github.com/meehow/python-xrandr/blob/master/xrandr/cli.py - I can't figure out how to flip VGA1 to mode 5 1024x768 (which works fine with xrandr) | 17:07 |
| tpb | Title: python-xrandr/cli.py at master · meehow/python-xrandr · GitHub (at github.com) | 17:07 |
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| _florent_ | Hi guys | 18:15 |
| _florent_ | I discovered your project 1 year ago and discussed with mithro some days ago by mail about it. | 18:15 |
| _florent_ | HDMI2USB seems really cool! and compressing video is one topic I'd like to work on, | 18:16 |
| _florent_ | I'm working at a lower level for now on litescope, liteeth and others stuff using Migen/MiSoC... | 18:16 |
| CarlFK | _florent_: have you done fpga things? | 18:16 |
| _florent_ | Mithro seems interested in sharing stuff between HDMI2USB and Migen/MiSoC so if some of you want to | 18:16 |
| _florent_ | reuse stuff we developed with M-Labs, feel free to ask or discuss with me :) | 18:17 |
| _florent_ | Hi CarlFK | 18:17 |
| CarlFK | hi | 18:17 |
| _florent_ | yes I'm a FPGA designer | 18:17 |
| CarlFK | cool - right now we are kinda stuck on getting the video in | 18:17 |
| CarlFK | er | 18:17 |
| CarlFK | getting the video in reliably | 18:17 |
| _florent_ | what are the issues you have? | 18:18 |
| CarlFK | we get it in most of the time, but too often the device does not show up, and then we have no idea whats going on | 18:18 |
| _florent_ | isn't it related to EDID? | 18:19 |
| CarlFK | they (not me, im just a user) suspect the edid isn't being done | 18:19 |
| CarlFK | that's the theory, but don't need better debugging tools to better understand it | 18:19 |
| CarlFK | er, don't have... need better | 18:20 |
| _florent_ | maybe you can try litescope :) | 18:20 |
| _florent_ | I know the m-labs that that worked on HDMI also had issue with EDID | 18:20 |
| CarlFK | oddly enough about 5 min ago I put my board on a shelf thinking "I wonder when I will have something to try" ;) | 18:21 |
| CarlFK | but im prolly not the person to be trying litescope | 18:22 |
| _florent_ | what FPGA are you using on HDMI2USB? | 18:22 |
| CarlFK | im just a cranky user ;) | 18:22 |
| CarlFK | sec... | 18:22 |
| cfelton | digilent Atlys board is one of the platforms | 18:23 |
| _florent_ | about the input video issue, here an HDMI input core developed by sb0 on m-labs: | 18:24 |
| _florent_ | http://git.io/N8E0 | 18:24 |
| tpb | Title: mixxeo-soc/mixxeolib/dvisampler at master · m-labs/mixxeo-soc · GitHub (at git.io) | 18:24 |
| _florent_ | it can maybe be interesting to had a look at what he did for EDID | 18:24 |
| _florent_ | it seems to be working reliably | 18:24 |
| CarlFK | http://code.timvideos.us/projects/hdmi2usb/ "For developing features for the HDMI2USB system we use a Digilent ATLYS prototype board." | 18:26 |
| tpb | Title: TimVideos.us Planet - Developers News (at code.timvideos.us) | 18:26 |
| CarlFK | Xilinx Spartan 6 LX45 FPGA | 18:26 |
| _florent_ | OK thanks, that's the same FPGA we are using on Mixxeo (the link I sent) | 18:27 |
| _florent_ | about the JPEG encoder, you are using one from Opencores or have you developed your own? | 18:29 |
| CarlFK | does that mean you can try these things you recommended i try? | 18:30 |
| cfelton | _florent_: it is the VHDL encoder from opencores | 18:30 |
| CarlFK | not sure - my guess is Opencores | 18:30 |
| _florent_ | Hi cfelton | 18:30 |
| CarlFK | yay - 2 people that can talk intelligently and I'll just listen now :) | 18:31 |
| cfelton | test and comparison (in complete of course) of the different jpegenc for opencores | 18:31 |
| cfelton | https://github.com/cfelton/test_jpeg | 18:31 |
| tpb | Title: cfelton/test_jpeg · GitHub (at github.com) | 18:31 |
| cfelton | http://opencores.org/project,mkjpeg | 18:33 |
| tpb | Title: JPEG Encoder :: Overview :: OpenCores (at opencores.org) | 18:33 |
| _florent_ | nice thanks, I will have a closer look at that! | 18:33 |
| cfelton | best I can tell, the VHDL version (mkjpeg) throughput is much less than the verilog version (http://opencores.org/project,jpegencode different designs) but the verilog version is incomplete, it needs line buffer etc. | 18:35 |
| tpb | Title: JPEG Encoder Verilog :: Overview :: OpenCores (at opencores.org) | 18:35 |
| _florent_ | I'd like to try a JPEG encoder on Mixxeo and do HDMI --> Ethernet (UDP) with LiteEth | 18:36 |
| cfelton | I recently converted majority of code to verilog (including mkjpeg) so they could use FOSS simulators if they want | 18:36 |
| cfelton | We had a GSoC last year that attempted HDMI --> Ethernet | 18:37 |
| _florent_ | yes mithro send me some documentation on that | 18:37 |
| _florent_ | nice for the verilog convertion, it must take some time... | 18:38 |
| cfelton | some but i have a process down so it goes fast http://www.fpgarelated.com/showarticle/718.php, unless I make a stupid mistake it can take some time to debug and find - the process is fairly error prone, not something I would want to do often | 18:40 |
| tpb | Title: I don’t often convert VHDL to Verilog but when I do ... (at www.fpgarelated.com) | 18:40 |
| _florent_ | thanks for the link :) | 18:41 |
| _florent_ | I see you are a MyHDL user, that should help a lot for your testbenchs :) | 18:46 |
| _florent_ | (even if I'm a Migen user...) | 18:47 |
| cfelton | I know | 18:48 |
| cfelton | odd days ahead | 18:49 |
| _florent_ | I have to go, thanks CarlFK and cfelton for the discussion, see you | 18:53 |
| CarlFK | see ya | 18:53 |
| cfelton | later | 19:11 |
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