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| shenki | cfelton: that's an interesting point about converting to verilog | 10:16 |
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| shenki | there's no hard requirement; it appears that the Vivado issue can be worked around. my VHDL is rusty enough that I don't know if their proposed solution would make us incompatable with ise | 10:17 |
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| cfelton | shenki: it looks like the work around would work, if there are no objects I am going to take a swag at converting it all to Verilog. | 13:32 |
| cfelton | for the reasons stated above, not that I necessarily prefer Verilog over VHLD but having a single lang source and the FOSS support seems reason enough | 13:32 |
| cfelton | mithro: https://github.com/cfelton/gizflo | 13:34 |
| tpb | Title: cfelton/gizflo ยท GitHub (at github.com) | 13:34 |
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