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| mithro | rohitksingh1: ping? | 02:55 |
|---|---|---|
| mithro | Joelw: ping? | 02:55 |
| Joelw | mithro: Hi! | 02:56 |
| mithro | Joelw: I was wondering if ChipScope could help with my RX issue | 02:56 |
| rohitksingh1 | mithro: Hi! | 02:56 |
| mithro | Joelw: I'm trying to debug why my computer doesn't see the RX port and should probably start with why it's not seeing the EDID information | 02:56 |
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| mithro | rohitksingh1: we ready to send of to production? | 02:56 |
| mithro | rohitksingh1: what do you need me to review? | 02:56 |
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| mithro | rohitksingh1: I also wanted to talk to you about I2C | 02:58 |
| rohitksingh1 | mithro: around 30% impedance matching is left. Please review the current board. Was unwell for 2 days. Made up the lost time in last 24 hours | 02:58 |
| mithro | rohitksingh1: okay | 02:58 |
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| rohitksingh | mithro: what did you want to talk about I2C? | 02:59 |
| mithro | rohitksingh: lets wait until after you've finished the PCB :) | 03:00 |
| Joelw | mithro: It can help! Just attach ChipScope to the EDID lines and capture a few thousand samples as soon as you see some activity? | 03:00 |
| mithro | rohitksingh: don't want to distract you | 03:00 |
| mithro | Joelw: "attach ChipScope" means the wires from the programmer or is that something in the FPGA? | 03:01 |
| Joelw | Oh! Haven't used it before? | 03:01 |
| Joelw | The easiest way is to use the ChipScope Core Inserter | 03:01 |
| Joelw | It lets you define a number of debug buses (each with independent clock and width) | 03:02 |
| Joelw | You select e.g. one bus, two bits wide - clock and data | 03:02 |
| rohitksingh | mithro: okay. Please review the current design. It has become pretty *dense* due to length matching. I hope it doesn't result in load capacitances greater than specified in datasheet | 03:02 |
| Joelw | Then attach that to your EDID clock and data lines by finding and selecting nets | 03:02 |
| mithro | Joelw: yes, never used ChipScope before | 03:02 |
| Joelw | Then it whirs away and you build your design, which takes 10 times longer than normal, and then ChipScope Pro will attach to the core over JTAG | 03:02 |
| Joelw | Requires the Digilent plugin or a proper Platform Cable USB - it won't work if you're using libfpgalink | 03:03 |
| mithro | Joelw: yes, got the fake Platform Cable USB from ebay | 03:03 |
| mithro | mparuszewski: ping? | 03:04 |
| mithro | wow, the github issue interface has changed | 03:07 |
| Joelw | mithro: Excellent! Yeah, try the inserter thing. You may have to use ISE for that. There are two ways you can use CSP - either as a thing that generates cores that you can instantiate in HDL and hook signals up to, or as a special inserter thing that you pick signals from the GUI and it magically inserts it during the build | 03:07 |
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| tvCommitBot | [HDMI2USB] mithro opened pull request #73: Adding `infrastructure` label to CONTRIBUTING document. (master...doc-add) http://git.io/szN0Lg | 03:20 |
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| mithro | Joelw: okay | 03:32 |
| mparuszewski | mithro: pong :) | 03:37 |
| mithro | mparuszewski: how's it going? | 03:38 |
| mithro | mparuszewski: a) deployment! :P b) wanted to chat more about the issues stuff c) we never got to c in our last chat and should do it | 03:38 |
| mparuszewski | I just woke up, but I am feeling good. How are you? :) | 03:43 |
| mparuszewski | About the deployment, could you fork prose editor to timvideos github? I will deploy everything. | 03:45 |
| shenki | mithro: nice work on the travis | 03:46 |
| shenki | mithro: you ended up working out how to encode the key i see | 03:46 |
| mparuszewski | I deployed gatekeeper, and I need only prose editor to make it working. :) Then I will update config files and deploy getting started. :) | 03:47 |
| mithro | shenki: yes - but I found this nifty thing that lets you set environment variables on a travis repo via the travis command rather than the .travis.yml file | 03:47 |
| mithro | shenki: which means we don't need to pollute .travis.yml file with secure environment variables for each user | 03:48 |
| mithro | shenki: turns out the ssh-key stuff only works on travis-pro | 03:48 |
| shenki | mithro: i see | 03:49 |
| mparuszewski | Yes, after creating Travis key we need to update Travis.yml file, commit to master and turn Travis on and that's it, everything should work now :) | 03:50 |
| mparuszewski | I can deploy the site, and update our deployment process file if I forgot about something | 03:52 |
| mithro | mparuszewski: can you link me to the deploy instructions again? | 03:53 |
| mparuszewski | https://docs.google.com/document/d/15MgQzPmFDXaD0V7h0G827fpRtsIgVg0ML0IMye3pyl4/edit?usp=docslist_api | 03:54 |
| tpb | Title: TimVideos Getting Started Deployment - Google Docs (at docs.google.com) | 03:54 |
| mithro | rohitksingh: it might be okay to just length match each "byte" of the system, then everything | 03:55 |
| mparuszewski | I can say something about the c) part. I created application called feedbook, it works like a supybot bot, but feedbook can notify about updates not only on IRC, but also on twitter, Facebook, via mail, and it is easy to extend if you want to have your own notifier. I wanted to create application with ability to extend just like plugins in Jekyll. :) | 03:57 |
| mparuszewski | After I do my last changes and fixes to feedbook, I will write whole documentation, how to run, how to configure, etc. | 03:58 |
| mithro | mparuszewski: yeah, that all sounds great and exactly what I wanted you to do :) | 03:59 |
| mithro | mparuszewski: I wanted to more talk about how it works | 03:59 |
| mparuszewski | I have small things to do: offline mode and of course google plus integration. :) | 03:59 |
| mithro | mparuszewski: and what features we want it to support for a "1.0" release | 03:59 |
| mithro | shenki: any idea of a way to automate the Xilinx tools install? | 04:01 |
| mparuszewski | The 1.0 release should be definitely stable, so what we need is more tests, then we need to have a stable API for notifiers | 04:01 |
| mithro | mparuszewski: 1.0 should be a "minimal this works for our use case but still kind of buggy" :) | 04:02 |
| mparuszewski | Yes, I know :) and what are you expecting from that application? Do you want to have some special features? :) | 04:03 |
| rohitksingh | mithro: All tracks length-matched! *finally* The target of 10mm was met. Except for 2 signals which are within 10mm all other signals are within 5mm, with most of them within 3mm. I've just pushed complete files. Kindly review them. Also gerber here: http://gerblook.org/pcb/3XmFG2RUHVTZepoifZbztj | 04:09 |
| tpb | Title: GerbLook (at gerblook.org) | 04:09 |
| mithro | mparuszewski: well, I'm not sure | 04:09 |
| mithro | rohitksingh: so, the hackvana guys mentioned that you might want to use bigger via's | 04:10 |
| rohitksingh | mithro: btw how do i fix that soldermask issue? the drill (from above gerber) looks fine to me | 04:10 |
| mithro | rohitksingh: look at the top soldermask -> http://gerblook.org/pcb/3XmFG2RUHVTZepoifZbztj#top-soldermask | 04:11 |
| tpb | Title: GerbLook (at gerblook.org) | 04:11 |
| mithro | rohitksingh: there should be holes where the VGA connectors are | 04:11 |
| mithro | rohitksingh: I think it's probably in your VGA module? | 04:12 |
| rohitksingh | mithro: actually, all the dimensions I'm using is from the rev01 board. So, probably they should work fine. | 04:12 |
| rohitksingh | mithro: yeah. I think the probably is with the VGA footprint module | 04:12 |
| rohitksingh | *problem | 04:12 |
| mithro | rohitksingh: okay, can you get the #hackvana people to review | 04:13 |
| mithro | rohitksingh: and then do a bit of research and find out if there is anyone in india who does rush 2-3 day orders for PCB | 04:13 |
| mparuszewski | And about b) I have checked many github issues applications, unfortunately there is no open source application for that, I can't improve existing solution to suits our needs. But I was testing waffle and it has ability to have issues from many repositories on one kanban table. :) | 04:13 |
| mithro | mparuszewski: interesting - I kind of despise their "waffle" / table interface | 04:14 |
| mithro | mparuszewski: can you make writing up some design documentation on feedbook ASAP? I want to understand how it works and if there is something to the internals that might need to be changed | 04:15 |
| mparuszewski | Ok, I will prepare today some diagrams and I will write something about it. :6 | 04:15 |
| mparuszewski | :) | 04:16 |
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| mparuszewski | Ok, so I will work on design documentation for feedbook and to make it stable and fully working. :) and I will deploy prose to GitHub pages and we will be able to deploy getting started page and then we will think about integration with planet. :) | 04:21 |
| mithro | mparuszewski: added a couple of questions to the deploy document | 04:24 |
| mparuszewski | I see, I will answer them today and update the document with links. :) | 04:24 |
| mithro | rohitksingh: I do think they are right about using bigger via's it'll make the board easier to make | 04:28 |
| mithro | mparuszewski: great | 04:28 |
| rohitksingh | mithro: PCB situation is really depressing for DIYers in India :/ Most of the local flatly refuse any prototype esp. from students. There is one which i used 2 years back. They have 15 days turnaround and 8 mils limit. The best I found in India is http://pcbpower.com/ . Have 3 working days turnaround time (at extra cost) http://awesomescreenshot.com/04738434be Technical capabiities http://pcbpower.com/technical-capabilities | 04:32 |
| rohitksingh | mithro: Did they tell any good(i mean standard) size for vias? | 04:32 |
| tpb | Title: PCB Power :: Place order | Awesome Screenshot (at awesomescreenshot.com) | 04:32 |
| mithro | rohitksingh: Don't tell them your a student - or I'm happy to call / talk to them | 04:32 |
| mithro | rohitksingh: maybe something like http://www.pcbpower.com/power-express ? | 04:35 |
| rohitksingh | mithro: even then they have 15 days turnaround time! I think best would be either PCBPower or hackvana itself. | 04:36 |
| rohitksingh | mithro: Yeah, the screenshot i showed you is for PowerExpress itself. 3 days turnaround. Normal is 5 days. | 04:36 |
| mithro | rohitksingh: wow, that is much cheaper then I expected | 04:37 |
| mithro | rohitksingh: does pcbpower specs meet your needs? | 04:37 |
| rohitksingh | mithro: from the link I gave u it seems so. Our design uses 4.92mils track and 0.3mm via drill. For standard they support 5mils, 0.25mm plated hole size (don't know whether its drill or via dia) and for Prototype they support 4mils tracks and 0.2mm plated hole size | 04:43 |
| rohitksingh | if the PowerExpress uses prototype specs then most probably our board is supported | 04:44 |
| mithro | rohitksingh: okay, lets see how fast we can get them from hackvana | 04:45 |
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| mithro | rohitksingh: can you call pcbpower and find out if they do the prototype specs for express orders? | 04:48 |
| mithro | rohitksingh: I'd like to get these boards out to production today if possible | 04:49 |
| mithro | "For Orders placed before 9 am, day of the order entered will be counted in delivery days. For orders placed after 9 am, the day of order will not be counted." | 04:49 |
| rohitksingh | mithro: Today is Gazetted Holiday here due to Islamic festival of Eid. So, they will be shut today. Can try tomorrow | 04:50 |
| mithro | rohitksingh: damn, okay | 04:50 |
| mithro | rohitksingh: please do talk to hackvana ASAP | 04:50 |
| mithro | (IE right now would be good :) | 04:50 |
| rohitksingh | mithro: okay. btw i can't seem to fix that soldermask. I've edited the module even then it shows up :/ | 04:52 |
| mithro | rohitksingh: people on #kicad and #hackvana might be able to help | 04:53 |
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| rohitksingh | mithro: Never mind! Fixed it! http://gerblook.org/pcb/XjthK9tt7D8suc8GHbhqw8 | 04:57 |
| tpb | Title: GerbLook (at gerblook.org) | 04:57 |
| rohitksingh | mithro: what shall I talk to hackvana about? reviewing PCB? or anything else too? | 05:05 |
| mithro | rohitksingh: ask him how fast he could turn around the PCB? | 05:05 |
| mithro | rohitksingh: tell him your my student | 05:05 |
| rohitksingh | mithro: okay! | 05:05 |
| mithro | rohitksingh: make sure you've read his FAQ | 05:06 |
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| mithro | rohitksingh1: are there any items still left in the issue tracker you haven't closed? | 05:09 |
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| rohitksingh | mithro: 5 bugs. 1 related to silkscreen | 05:10 |
| rohitksingh | Should i close that one? | 05:10 |
| rohitksingh | https://github.com/rohit91/HDMI2USB-vmodvga/issues | 05:10 |
| tpb | Title: Issues · rohit91/HDMI2USB-vmodvga · GitHub (at github.com) | 05:10 |
| rohitksingh | mithro: Issue #8 was fixed quite a while back. Same with Issues #15 and #13. Should I just close them directly? | 05:18 |
| mithro | rohitksingh: yes | 05:18 |
| rohitksingh | okay, great | 05:19 |
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| rohitksingh | mithro: you are needed on hackvana channel | 06:01 |
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| mithro | rohitksingh: lets skip our 1:1 today and just concentrate on getting hackvana the design | 06:43 |
| mithro | Joelw: just starting to get going with the ChipScope now, I loaded the project in ISE and then double clicked the "Analyze the design with ChipScope" - now waiting for it to do stuff | 06:45 |
| rohitksingh | mithro: Okay. You just caught the words from my mouth! :) I was going to request relaxation on Weekly Report, as I haven't got time to write it yet. Will share it later today! | 06:45 |
| mithro | rohitksingh: your weelky report can be "I sent the board to Hackvana for production" :) | 06:45 |
| Joelw | Excellent! :) | 06:47 |
| rohitksingh | mithro: Great! :) | 06:47 |
| mithro | Joelw: but now my design fails the map phase, trying to figure out why | 06:48 |
| Joelw | If you have a big design and you try to add a CSP core with 128K sample depth, it won't be able to fit it all | 06:53 |
| Joelw | It can get upset if the signals in a probe are in different clock domains too, though I don't recall if that causes a map failure | 06:53 |
| Joelw | Oh, this book just came out: http://www.amazon.com/The-Zynq-Book-Processing-Programmable/dp/099297870X/ref=sr_1_1?ie=UTF8&qid=1406616860&sr=8-1&keywords=the+zynq+book | 06:54 |
| Joelw | Surprisingly affordable for an FPGA book! | 06:54 |
| Joelw | The only problem is that shipping is $10 and if I spend $5 more, I get free shipping. However I can't find anything for $5 that I want that isn't a Kindle book | 06:57 |
| mithro | Joelw: I just double clicked the button | 07:00 |
| rohitksingh | Joelw: Did you see this book. Released just few days back. Free Ebook. http://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-Book-Free-PDF-or-27-paper-version-Your-choice-Get-them/ba-p/495600 | 07:01 |
| tpb | Title: The Zynq Book: Free PDF or $27 paper version. Your... - Xilinx User Community Forums (at forums.xilinx.com) | 07:01 |
| Joelw | rohitksingh: Cool thanks - I'll just download it and save $30! :) | 07:02 |
| rohitksingh | Joelw: Welcome! :) | 07:07 |
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| rohitksingh | mithro: How can i contact you then, if some need arises? | 08:05 |
| rohitksingh | mithro: you mean after reaching home, you'll again be accessible on laptop? | 08:06 |
| mithro | rohitksingh: see private messages | 08:11 |
| rohitksingh | mithro: Got it! | 08:12 |
| mithro | Try all three :) | 08:15 |
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| rohitksingh | mithro: pushed the latest commit. Changed vias spec to 0.6mm dia, 0.3mm drill. Also fixed capacitor silkscreen and width of power supply pins going into IC. | 08:45 |
| rohitksingh | mithro: http://gerblook.org/pcb/43uf8aQpNunR4iV6mEkpvV | 08:45 |
| tpb | Title: GerbLook (at gerblook.org) | 08:45 |
| mithro | Okay | 08:48 |
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| mithro | Joelw: there appears to be some issues with io levels | 08:49 |
| mithro | will look at further later | 08:50 |
| rohitksingh | mithro: please have a look at this http://gerblook.org/pcb/aeBadGHdkgXt3yi92bWdgT#front | 09:10 |
| tpb | Title: GerbLook (at gerblook.org) | 09:10 |
| rohitksingh | with top copper pour and all other suggestions | 09:10 |
| rohitksingh | mithro: hackvana says "You'll want to be sending me your design pretty soon." | 09:11 |
| mithro | rohitksingh: yeap | 09:12 |
| rohitksingh | mithro: shall I send him the designs through mail? | 09:33 |
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| rohitksingh | mithro: "git push --tags" says "Everything up-to-date". yet "git describe" says "TwoVGAConn-56-g80a15f4"...Is this because I'm using gsoc branch not master branch? | 10:18 |
| mithro | rohitksingh: what does that git-describe command I sent you say? | 10:18 |
| mithro | rohitksingh - turns out that shenki has a BeagleBone not a BeagleBoneBlack - Can we still use it to test your board? | 10:19 |
| rohitksingh | "git describe" says "TwoVGAConn-56-g80a15f4 "whereas "git describe --tags --dirty --long" gives correct output "rev02_lengthMatched_w/o_topCopperPour-4-g80a15f4" | 10:19 |
| mithro | rohitksingh: how did you end up with the name vgaExp_v02_g50467ca.zip ? | 10:21 |
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| rohitksingh | mithro: yeah. you can still use it. If you require convenience rather than detailed debug output from python script running on BeagleBone, then I'll fix the I2C within few days. | 10:22 |
| rohitksingh | mithro: ah. I just used the last code. <Filled with shame> :P | 10:22 |
| rohitksingh | mithro: that last code was before I pushed again. | 10:23 |
| mithro | rohitksingh: ahh, you should tag that commit with "v02" I think | 10:24 |
| rohitksingh | okay...tagging it now. | 10:24 |
| rohitksingh | mithro: done and pushed the tag https://github.com/rohit91/HDMI2USB-vmodvga/releases/tag/v02 | 10:26 |
| tpb | Title: Release v02 · rohit91/HDMI2USB-vmodvga · GitHub (at github.com) | 10:26 |
| mithro | rohitksingh: I think we probably should clean up your tags shortly | 10:26 |
| rohitksingh | mithro: yeah. those were temporary ones | 10:27 |
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| tija | shenki: https://github.com/ajitmathew/HDMI2USB/commits/ajit-debug-v3 | 11:36 |
| tpb | Title: Commits · ajitmathew/HDMI2USB · GitHub (at github.com) | 11:36 |
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| shenki | tija: looks good | 13:07 |
| shenki | tija: i made some comments | 13:08 |
| shenki | tija: watching hockey? | 13:25 |
| shenki | tija: 2-0 already :D | 13:26 |
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| tvCommitBot | [HDMI2USB] shenki closed pull request #49: Initial debug module for HDMI2USB firmware (master...debug) http://git.io/iWWCxA | 14:49 |
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| tvCommitBot | [HDMI2USB] shenki closed pull request #70: Adding script to flash firmware using flcli/fx2loader. (master...flash) http://git.io/wXVa3w | 14:51 |
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| tvCommitBot | [HDMI2USB] shenki closed pull request #71: Adding Travis-CI building. (master...shenki-travis-test) http://git.io/jzQpJg | 14:51 |
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| tvCommitBot | [HDMI2USB] shenki closed pull request #73: Adding `infrastructure` label to CONTRIBUTING document. (master...doc-add) http://git.io/szN0Lg | 14:52 |
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| shenki | mergetastic | 14:53 |
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| skay | mithro: hi, for the bugtracker, are you going to set up an ec2 server for Niharika to use so that she can deploy the app? | 15:51 |
| skay | mithro: I have a fabfile that we can use to deploy things, and for that she needs an account with sudo | 15:52 |
| mithro | skay: I should be asleep, but we can do that | 15:52 |
| skay | mithro: oh! go to sleep. for the moment I have the fabfile working against a vagrant box | 15:52 |
| mithro | skay: would it make sense to just deploy it on the same server the main website? | 15:52 |
| skay | mithro: I'm not experienced with deploying multiple apps to one server... I might need help with the nginx conf | 15:54 |
| mithro | skay: where is the code? | 15:55 |
| skay | (or apache, if you are using apache. I'd need more help with that) | 15:55 |
| skay | mithro: in my fork, https://github.com/codersquid/bugtracker in a branch called fabric_example | 15:56 |
| tpb | Title: codersquid/bugtracker · GitHub (at github.com) | 15:56 |
| skay | and keep in mind that I'm not that experienced in ops stuff, so it's sloppy | 15:56 |
| skay | and still in progress. I've only used fabric for some months now and never really got good at it | 15:57 |
| skay | haven't needed to | 15:57 |
| skay | if you have suggestions for making it better that would be great | 15:57 |
| skay | you could leave comments in my PR https://github.com/Niharika29/bugtracker/pull/8 | 15:58 |
| tpb | Title: Fabric code for deploying the site to a vagrant box by codersquid · Pull Request #8 · Niharika29/bugtracker · GitHub (at github.com) | 15:58 |
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| skay | Niharika: I forgot to add the fabric and fabtools dependencies to the requirements file for vagrant, so things will fail when you try to use the `fab` command. I apologize! | 16:12 |
| Niharika | skay: It´s okay. I´m poking around. | 16:13 |
| skay | and I'm not actually certain where the best place for those two is. maybe they should be somewhere else | 16:13 |
| skay | I added some comments to the PR for it | 16:13 |
| Niharika | Okay! | 16:13 |
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| tija | shenki: https://github.com/ajitmathew/HDMI2USB/commit/e96fb590dd78bc23c80d373d0845f45856d99592 | 22:16 |
| tpb | Title: Memory Read and Write Pipeline · e96fb59 · ajitmathew/HDMI2USB · GitHub (at github.com) | 22:16 |
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| Joelw | mithro: I/O levels with CSP? | 23:21 |
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