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| mithro | CARAM_: ping? | 00:06 |
|---|---|---|
| mithro | aps-sids: ping? | 00:06 |
| mithro | mparuszewski: ping? | 00:06 |
| mithro | tariq786: ping? | 00:06 |
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| mithro | ayush3504: how's the PCB going? | 00:28 |
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| mithro | hi rohitksingh, how's the VGA requirements going? | 01:04 |
| rohitksingh | mithro: morning! :) Its 6:35AM here. Will resume it after breakfast! | 01:05 |
| mithro | rohitksingh: no worries | 01:05 |
| puck | mithro: Cool. | 01:14 |
| rohitksingh | mithro: for EDID support for both VGA Source(PC) and VGA Sink(Monitor), we need 4 extra pins (2 I2C lines for each of them). I think I can free upto 3 pins only (OE, COAST and CLAMP ones) | 01:22 |
| mithro | what is the VGA chip we are using again? | 01:23 |
| rohitksingh | AD9984A | 01:23 |
| rohitksingh | okay I see we can free one more pin we don't use PWRDN pin. | 01:24 |
| mithro | Looking at the functional diagram at http://www.analog.com/en/audiovideo-products/analoghdmidvi-interfaces/ad9984a/products/product.html | 01:24 |
| tpb | Title: AD9984A datasheet and product info | High Performance 10-Bit Display Interface | Analog/HDMI/DVI Interfaces | Analog Devices (at www.analog.com) | 01:24 |
| mithro | The chip seems to support SDA/SCL interface internally? | 01:25 |
| rohitksingh | Yes, we need 2 I2C pins separate for AD9984A | 01:25 |
| mithro | rohitksingh: so the AD9984A doesn't have any EDID interface on it? | 01:26 |
| rohitksingh | mithro: No. Its only for initialization and configuration. No inbuilt EDID support | 01:27 |
| mithro | rohitksingh: okay, I hadn't realised that | 01:27 |
| rohitksingh | mithro: I've got an idea...We can hook both AD9984A and the Sink's I2C Lines to same bus | 01:27 |
| rohitksingh | at sink would be at 0x50 and the AD9984A would be at 0x4C | 01:28 |
| mithro | rohitksingh: there are multiple possibilities like that too.... | 01:28 |
| rohitksingh | Or, I could simply not use PWRDWN pin, and pull it to ground permanently | 01:29 |
| mithro | rohitksingh: where's the pin mapping spreadsheet again? | 01:31 |
| rohitksingh | Here https://docs.google.com/spreadsheets/d/1f-rBfR98f_ZZNIB7GFV79CGSHQNpj47uOU0JDwOJnV8/edit#gid=62369278 | 01:32 |
| tpb | Title: Atlys Expansion Boards Information (using VHDCI connectors) - Google Tabellen (at docs.google.com) | 01:32 |
| mithro | rohitksingh: can you fill out the "description" column? | 01:33 |
| rohitksingh | mithro: yeah. | 01:34 |
| mithro | I also think the EDID lines are 5V verse the 3.3V the FPGA provides? | 01:35 |
| rohitksingh | mithro: This page mentions 5V! http://www.extron.com/company/article.aspx?id=uedid&version=print | 01:39 |
| tpb | Title: Extron Electronics - Understanding EDID - Extended Display Identification Data (at www.extron.com) | 01:39 |
| rohitksingh | So, We need separate lines for AD9984A, VGA Source and VGA Sink | 01:39 |
| rohitksingh | mithro: The Power Down feature is accessible through AD9984A's registers also. So we can remove the PWRDWN pin | 01:43 |
| rohitksingh | coming back in 10 minutes | 01:44 |
| mithro | okay, no hurry | 01:44 |
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| mithro | rohitksingh: SERIAL CONTROL PORT The serial control port is designed for 3.3 V logic; however, it is tolerant of 5 V logic signals. Refer to the 2-Wire Serial Control Port section for more information. | 01:56 |
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| rohitksingh1 | mithro: i don't think spartan 6 can tolerate 5V? let me check | 01:59 |
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| rohitksingh | mithro: yeah spartan 6 pins are not 5V tolerant | 02:04 |
| mithro | heading to lunch, be back later | 02:05 |
| Joelw | I think the TMDS141 chip on the Atlys does I2C level conversion. For the unbuffered HDMI connectors, I would be a bit wary about the 5V going straight to the FPGA! | 02:06 |
| Joelw | They do go via the series 50R resistor though. | 02:06 |
| rohitksingh | Joelw: Thanks for the info! Thats what i was wondering that how is HDMI's I2C handled | 02:08 |
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| shenki | o/ | 03:10 |
| shenki | ive just been reviewing tija's pull request, and it got me thinking about the formatting of our hdl | 03:11 |
| shenki | what editors are people using to write their verilog/vhdl? | 03:11 |
| mithro | shenki: yeah, that is something I've been holding off on defining | 03:17 |
| mithro | shenki: but we really should have a consistent code style + programmatic checking of code style | 03:17 |
| shenki | mithro: yeah | 03:19 |
| shenki | mithro: im not proposing to reformat existing code | 03:19 |
| shenki | mithro: but as people write new modules, it would be good to do something | 03:19 |
| shenki | i used to use emacs to format my code | 03:19 |
| shenki | I'd write it in vim (the one true editor), and then run it through emacs to get the style correct | 03:20 |
| mithro | The best tool I know for linting Verilog is Verilator. Check the --lint-only option if you don't need the simulation. | 03:20 |
| mithro | from a stack overflow post | 03:20 |
| shenki | ok | 03:21 |
| mithro | http://www.veripool.org/wiki/verilator | 03:21 |
| tpb | Title: Intro - Verilator - Veripool (at www.veripool.org) | 03:21 |
| mithro | http://covered.sourceforge.net/ | 03:25 |
| tpb | Title: Covered - Verilog Code Coverage Analyzer (at covered.sourceforge.net) | 03:25 |
| mithro | Not a lint tool, but a coverage analyzer | 03:25 |
| mithro | http://cdn.opencores.org/downloads/opencores_coding_guidelines.pdf | 03:26 |
| shenki | mithro: so ive reviewed tija's patch | 03:31 |
| shenki | mithro: i split it up into 4 separate patches | 03:31 |
| shenki | i guess I should have gotten him to do that, but I wanted to get stuck into the the code, and it was the most obvious way to make it happen | 03:31 |
| shenki | it looks good, aside from not matching the existing style in the files he modified (i fixed that up) | 03:32 |
| shenki | and there's one line that snuck in that shouldn't be there - i think it's from tija playing with the encoding quality | 03:32 |
| shenki | mithro: we also need to settle on a copyright header | 03:34 |
| shenki | some of the existing ones are a bit... excessive | 03:34 |
| mithro | http://bear.ces.cwru.edu/tools.html | 03:39 |
| tpb | Title: VLSI CAD Group Index of Useful Tools (at bear.ces.cwru.edu) | 03:39 |
| mithro | VHDL-NICE93 : a VHDL-93 beautifier. This is source with LINUX & SunOS binaries. | 03:39 |
| mithro | VHDL-NICE : a VHDL-87 beautifier. This is source with LINUX binaries. | 03:39 |
| shenki | SunOS ftw | 03:44 |
| shenki | here is my fixed up version of tija's code: https://github.com/shenki/HDMI2USB/tree/ajit-debug | 03:45 |
| tpb | Title: shenki/HDMI2USB at ajit-debug · GitHub (at github.com) | 03:45 |
| mithro | shenki: that is the limit of what I found via Google | 03:46 |
| shenki | ok | 03:46 |
| shenki | mithro: did you discuss much more with tija after i left last night? | 03:47 |
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| mithro | http://www.stack.nl/~dimitri/doxygen/ seems to support VHDL as a source language | 03:48 |
| tpb | Title: Doxygen: Main Page (at www.stack.nl) | 03:48 |
| mithro | doxverilog | 03:49 |
| mithro | appears to be a version of doxygen which supports verilog | 03:49 |
| mithro | http://checkstyle.sourceforge.net/index.html seems to support some "language agnostic" checking | 03:51 |
| tpb | Title: checkstyle - Checkstyle 5.7 (at checkstyle.sourceforge.net) | 03:51 |
| mithro | but it's horrible java | 03:51 |
| shenki | im not very interested in imposing doxygen on anyone | 03:51 |
| mithro | shenki: have you heard of or used SonarQube? | 04:00 |
| mithro | http://astyle.sourceforge.net/ seems to do a bunch of c style languages | 04:14 |
| tpb | Title: Artistic Style - Index (at astyle.sourceforge.net) | 04:14 |
| mithro | Emacs VHDL-mode has a beautify-buffer command, which works well and is very configurable. I use this all the time | 04:15 |
| mithro | http://search.cpan.org/~mykl/Hardware-Vhdl-Tidy-0.8/lib/Hardware/Vhdl/Tidy.pm | 04:16 |
| tpb | Title: Hardware::Vhdl::Tidy - search.cpan.org (at search.cpan.org) | 04:16 |
| mithro | http://www.vim.org/scripts/script.php?script_id=1450 | 04:16 |
| tpb | Title: VHDL indent ('93 syntax) - Revised VHDL indent file : vim online (at www.vim.org) | 04:16 |
| mithro | emacs -batch file.v -l vindent.el -kill >& /dev/null & | 04:20 |
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| shenki | emacs -batch hdl/DEBUG/counter_top.vhd -f vhdl-beautify-buffer -f save-buffer | 04:30 |
| shenki | that's how i do it for vhdl | 04:30 |
| shenki | mithro: i think a friend uses sonarqube for java | 04:31 |
| shenki | or something similar | 04:31 |
| mithro | yeah | 04:34 |
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| shenki | tija: hey | 07:05 |
| shenki | tija_: hey | 07:05 |
| tija_ | shenki: Hi! | 07:08 |
| tija_ | shenki: It seems that the ddr is reading and writing only useful pixels. So no worries in that area. | 07:15 |
| shenki | tija_: good news | 07:20 |
| shenki | tija_: i took a look at your pull request | 07:20 |
| shenki | tija_: some feedback for you: it's often good to split large commits up into smaller, logical cunks | 07:20 |
| shenki | chunks | 07:21 |
| shenki | it makes it much easier for others to review | 07:21 |
| shenki | to demonstrate, i did it for you :) | 07:21 |
| shenki | https://github.com/shenki/HDMI2USB/commits/ajit-debug | 07:21 |
| tpb | Title: Commits · shenki/HDMI2USB · GitHub (at github.com) | 07:21 |
| shenki | tija_: i also tidied up some of the changes to existing files so the changes matched the existing coding style | 07:22 |
| tija_ | shenki: okay understood, i created a new branch and dumped all the changes to it together. Next time I will take care. | 07:23 |
| shenki | tija_: that's fine | 07:23 |
| shenki | tija_: as far as the brand new files goes, it would be good to follow some kind of coding style | 07:23 |
| shenki | tija_: what editor do you use? | 07:23 |
| tija_ | shenki: the one in ISE. | 07:23 |
| shenki | ok | 07:24 |
| shenki | does it format the code for you? | 07:24 |
| shenki | or is it free form? | 07:24 |
| tija_ | shenki: I find it easier to debug using it. Yes it formates the code. | 07:24 |
| shenki | ok | 07:25 |
| tija_ | shenki: what do you use? | 07:25 |
| shenki | i ran your code through emacs code formatting when i committed it, as i like the way it formats the assignment operators with indents | 07:25 |
| shenki | https://github.com/shenki/HDMI2USB/commit/3e1a63bca970d9599995e76c276f43cbdd57a508 | 07:26 |
| tpb | Title: Add debug module · 3e1a63b · shenki/HDMI2USB · GitHub (at github.com) | 07:26 |
| shenki | you can kind of script it without having to open up emacs | 07:26 |
| shenki | emacs -batch hdl/DEBUG/counter_top.vhd -f vhdl-beautify-buffer -f save-buffer | 07:26 |
| tija_ | shenki: oh yeah it looks pretty! Which editor you use while coding? | 07:28 |
| shenki | tija_: i use vim | 07:28 |
| shenki | to be honest, i haven't done much vhdl since finishing uni 4 years ago | 07:28 |
| shenki | but i write all of my python and c in vim | 07:29 |
| tija_ | shenki: for python and C I use vim. I use ISE because as soon as you save files you get error messages on ISE terminal. | 07:30 |
| shenki | that's handy | 07:31 |
| shenki | a contractor i worked with at my last job used ghdl and vim | 07:32 |
| shenki | and drove it all with python and make | 07:32 |
| shenki | so you could code similar to with c: type, save, make | 07:32 |
| shenki | and get warnings | 07:32 |
| shenki | and then you only needed to fire up the xilinx or altera tools when synthesising for the device | 07:32 |
| shenki | tija_: would you like to submit a talk on your project to an open source conference? | 07:33 |
| shenki | tija_: linux.conf.au | 07:34 |
| tija_ | shenki: On the optimisation work I am doing? | 07:34 |
| shenki | yeah | 07:34 |
| shenki | perhaps make it a bit more general about doing open hardware development for FPGAs | 07:34 |
| shenki | but use your project as a case study | 07:35 |
| shenki | the reason i think it will be a good talk is that many people at the conference will have a Novena, the open source laptop | 07:35 |
| shenki | which contains a FPGA | 07:35 |
| shenki | so lots of programmers will be keen to get their hands dirty with FPGAs, perhaps for the first time | 07:35 |
| tija_ | yeah that would be great. Plus there are lot of open source fpga platform coming up like arduinos | 07:36 |
| tija_ | have you tried papilio? | 07:36 |
| mithro | shenki: https://github.com/mithro/hdl-pretty | 07:39 |
| tpb | Title: mithro/hdl-pretty · GitHub (at github.com) | 07:39 |
| tija_ | mithro: that is for formatting vhdl/verilog? | 07:42 |
| tija_ | okay yes it is for formating | 07:43 |
| shenki | mithro: nice | 08:00 |
| shenki | tija_: what is papililo? (I guess that means i haven't tried it) | 08:00 |
| mithro | papililo | 08:01 |
| mithro | opps | 08:01 |
| mithro | http://papilio.cc/ | 08:01 |
| tpb | Title: Papilio FPGA Platform (at papilio.cc) | 08:01 |
| shenki | ah | 08:02 |
| shenki | tiny fpga :) | 08:02 |
| shenki | not cheap | 08:02 |
| shenki | this is an interesting board: http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO | 08:04 |
| tpb | Title: Digilent Inc. - Digital Design Engineer's Source (at www.digilentinc.com) | 08:04 |
| shenki | Adding HDMI ports would make that a very beefy HDMI2USB v2 | 08:04 |
| shenki | as it's got a Cortex A9 @ 650MHz | 08:05 |
| shenki | two arm cores | 08:05 |
| shenki | and DDR3 | 08:05 |
| shenki | gigabyte ethernet | 08:05 |
| shenki | it's double the price of the papilio | 08:07 |
| shenki | but far more than double the functioanlity | 08:07 |
| tija_ | papilio is meant for hobbyist and is open source. It is more like arduino. | 08:08 |
| tija_ | shenki: Can you point me to the license I am suppose to add here. https://github.com/shenki/HDMI2USB/commit/df90a3bc55738991e0f31b0e9498e82e2f231001 | 08:13 |
| tpb | Title: Add UART to design · df90a3b · shenki/HDMI2USB · GitHub (at github.com) | 08:13 |
| Joelw | Yep! If I were designing a new board, I'd probably try to use a Zynq :) | 08:13 |
| Joelw | They're fairly expensive and BGA only though. | 08:13 |
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| mithro | shenki: Have you seem Joelw's page of low cost FPGA solutions? | 08:23 |
| Joelw | I haven't added some of the new Digilent ones :( They've released a few recently but apparently didn't announce them anywhere. | 08:39 |
| shenki | mithro: what licence are we using for hdmi2usb? | 08:54 |
| shenki | tija_: did you write all of the code that you added in the patch? or is some copied? | 08:54 |
| tija_ | shenki: I did not write the UART fifo. Took it from an old project we did in college. | 08:59 |
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| shenki | doh, he's gone | 09:06 |
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| tija | shenki: I am back. | 09:15 |
| aps-sids | mithro: Do we have a version of https://github.com/timvideos/gst-plugins-dvswitch for gst-1.0 | 09:15 |
| tpb | <http://ln-s.net/:5$r> (at github.com) | 09:15 |
| shenki | tija: hrm. the ones from college, do you have permission to open source them? | 09:24 |
| tija | It was for a course project, I guess we can use it the way we like. | 09:25 |
| shenki | ok | 09:27 |
| shenki | the other code is licensed MIT | 09:27 |
| shenki | so we probably want to do the same for yours | 09:28 |
| shenki | add a simple header that has `Copyright 2014 Joel Stanley <[email protected]>` at the top | 09:29 |
| shenki | except with your name and email | 09:29 |
| tija | okay | 09:30 |
| mithro | aps-sids: no | 09:43 |
| mithro | aps-sids: want to give it a whirl? | 09:44 |
| aps-sids | mithro: so I cannot port that component right? | 09:44 |
| mithro | aps-sids: micolous and thaytan did the initial code | 09:44 |
| aps-sids | yeah, I can try | 09:44 |
| mithro | shenki: http://www.zedboard.org/product/microzed | 09:51 |
| tpb | Title: MicroZed | Zedboard (at www.zedboard.org) | 09:51 |
| mithro | any idea how the Atrix-7 compare to the Spartan-6 FPGAs? | 09:55 |
| mithro | The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. | 10:01 |
| mithro | Interesting solution -> https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830&PartNo=1 | 10:08 |
| tpb | Title: Terasic - All FPGA Main Boards - Cyclone V - Cyclone V GX Starter Kit (at www.terasic.com.tw) | 10:08 |
| shenki | mithro: i used one of those | 10:12 |
| shenki | mithro: i evaluated the platform for a work project | 10:12 |
| mithro | shenki: it seems to have inbuilt GTPs which are only available on the LX45T series Spartan-6s? | 10:12 |
| shenki | ok. i wasn't looking at the GTPs | 10:19 |
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| micolous | my ears are burning | 10:58 |
| micolous | Yeah, gst-plugins-dvswitch is the dodgeyest hackup of the udp plugin I could do to make it talk dvswitch ;) | 10:58 |
| micolous | But it worked which is the scary part. | 10:58 |
| micolous | dvswitch protocol is pretty simple, you send a hello message (it's some 4 byte magic documented in protocol.h if I recall) and it just sends you DV | 10:59 |
| micolous | then you use the DV demuxer in gstreamer to do the hard work | 10:59 |
| micolous | all you need to do is let gstreamer know when your tcp connection drops | 10:59 |
| micolous | So yeah, your plugin doesn't even need to know DV, it just needs to tell gstreamer it's getting DV | 11:00 |
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