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| tpb | <mithro> Yay - https://www.crowdsupply.com/great-scott-gadgets/luna | 01:02 |
|---|---|---|
| tpb | <tpb> Title: LUNA | Crowd Supply (at www.crowdsupply.com) | 01:02 |
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| peterb | hello, i've got something which is probably a beginner's question and i hope i am at the right place here. | 09:35 |
| peterb | few days ago, i've started looking into FPGA development using only open source toolchains: | 09:35 |
| peterb | first i got an iCEstick, built the icestorm tools and was able to "compile" a few simple Verilog examples (yosys; arachne-pnr; icepack; iceprog) and run them on the iCEstick hardware. hooray! | 09:35 |
| peterb | then i was aiming at SymbiFlow: using the info in symbiflow-examples.readthedocs.io i managed to install SymbiFlow, built some of the examples for Artix-7 / Arty 35T and even compiled another own Verilog example down to "top.bit". (my arty board has not arrived yet, so i could not run any examples on the real hardware yet.) | 09:36 |
| peterb | the next step that i am aiming for is to target ice40 using SymbiFlow instead of plain icestorm. (why? to use the identical toolchain both for xc7 and ice40. and maybe at one point even be able to compile the same verilog file to bitstreams for Arty A7 and iCEstick with the same toolchain.) | 09:36 |
| peterb | but now i'm stuck: the example documentation (symbiflow-examples.readthedocs.io) only talks about Artix-7 and EOS-S3, but not ICE40. as far as i understand it, i need architecture definitions for ice40, ideally pre-built ones like those provided for Artix-7 and EOS-S3. i could not find any, so i tried my luck installing symbiflow-arch-defs but have | 09:36 |
| peterb | no real clue what to do with the stuff in that repository. | 09:36 |
| peterb | can anyone help me? is my goal -- ice40 with SymbiFlow toolchain -- supported? if yes, how do i do it? can i get pre-built architecture definitions for ice40 somewhere? | 09:36 |
| sf-slack1 | <kgugala> it is (somehow) supported, but not really tested extensively | 09:37 |
| sf-slack1 | <kgugala> I assume it has many bugs | 09:37 |
| peterb | that's good to know | 09:38 |
| sf-slack1 | <kgugala> icestorm (with nextpnr) will be a better choice for ice40 FPGAs | 09:39 |
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| peterb | so would the recommendation be to use SymbiFlow when targeting xc7 and the icestorm tools directly when targeting ice40? and then set up the build process that the right tools are used for the chosen target architecture? | 09:40 |
| peterb | i had no background knowledge about SymbiFlow so far, but had read "Currently, it targets the Xilinx 7-Series, Lattice iCE40, Lattice ECP5 FPGAs, QuickLogic EOS S3 and is gradually being expanded to provide a comprehensive end-to-end FPGA synthesis flow." as the headline on symbiflow.github.io | 09:41 |
| peterb | that's why i assumed that my goal might be supported "out of the box" | 09:41 |
| tpb | <tnt> peterb: edalize might be able to abstract that for you | 09:41 |
| peterb | @tpb | 09:43 |
| peterb | @tpb thanks for the hint -- i did not know edalize. looks good on first sight | 09:43 |
| sf-slack1 | <pgielda> Symbiflow is an umbrella project to improve the state of open source FPGA (and ASIC somewhat as some tools overlap) tool(chains) | 10:29 |
| sf-slack1 | <pgielda> For Xilinx it uses VPR by default as place & route tool. But you can also use nextpnr -- and there is ongoing work on interchange format that make tools more interoperablr | 10:30 |
| sf-slack1 | <pgielda> The whole idea of open source is that you have freedom to mix and match | 10:30 |
| sf-slack1 | <pgielda> Obviously it would be great to improve/add better support for Lattice in VPR but for now nextpnr is more production ready | 10:31 |
| sf-slack1 | <pgielda> For Xilinx Series-7 VPR works great and if something does not work you can open an issue and we will try to fix it hopefully. | 10:31 |
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| sf-slack1 | <rodrigomelo9> Hi peterb. I had been working on https://github.com/PyFPGA/symbiflow_cli, a proof-of-concept that has the intention of unifying the flows that you described, and others. Currently, it supports ice40 and ECP5 devices. Moreover, it also supports VHDL, not Verilog only. | 11:39 |
| sf-slack1 | <rodrigomelo9> I was extremely busy at work, but the idea is to add support for Xilinx and Quicklogic devices in the near future. These flows are using VPR and are a little more complex than NextPNR, need more options, of course, for more advanced devices. | 11:42 |
| sf-slack1 | <rodrigomelo9> An extra feature is that it supports the employment of OCI containers, so if you have docker installed, you don't need to install anything more ;) Could be useful to have somebody using/testing it, reporting issues, etc. | 11:44 |
| -_whitenotifier-1cee- [fpga-interchange-tests] acomodi opened issue #52: Conflicts when cell name equals its cell type - https://git.io/JWr6r | 13:12 | |
| peterb | thanks @pgielda and @rodrigomelo9 for the further clarifications and the information about symbiflow_cli -- i'll have a look | 13:56 |
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| -_whitenotifier-1cee- [fpga-interchange-schema] reillymck opened issue #60: Get Conns for Wires - https://git.io/JWo96 | 15:38 | |
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| tpb | <mithro> https://ci.betrusted.io/betrusted-soc/doc/engine.html is very pretty | 17:32 |
| tpb | <tpb> Title: ENGINE — LiteX SoC Project documentation (at ci.betrusted.io) | 17:32 |
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