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| sf-slack | <ajinkyaraghuwanshi> Hello guys, I am having a problem : | 13:36 |
|---|---|---|
| sf-slack | <ajinkyaraghuwanshi> Hello I am having a problem : I have create a test that I have synthesised from yosys but I am trying to place and route it in vivado: | 13:37 |
| sf-slack | <ajinkyaraghuwanshi> ```Vivado% read_edif adder.edf /home/ajinkya/GSOC2021/github_symbiflow/symbiflow-arch-defs/xc/xc7/tests/2_bit_bcd_adder/adder.edf Vivado% create_project -part XC7A35TICSG324-1L -force adder adder Vivado% read_xdc basys3.xdc /home/ajinkya/GSOC2021/github_symbiflow/symbiflow-arch-defs/xc/xc7/tests/2_bit_bcd_adder/basys3.xdc Vivado% place_design Command: place_design 0 Infos, 0 Warnings, 0 Critical Warnings and 1 Errors | 13:38 |
| sf-slack | encountered. place_design failed ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. Vivado% ``` | 13:38 |
| sf-slack | <ajinkyaraghuwanshi> Can anybody guide me? | 13:38 |
| tpb | <gatecat> ajinkyaraghuwanshi: have a look at https://github.com/YosysHQ/yosys/blob/master/examples/basys3/run_vivado.tcl | 13:39 |
| tpb | <gatecat> in particular, I think you're missing a call to link_design after reading it in | 13:39 |
| sf-slack | <ajinkyaraghuwanshi> Ok I will try | 13:40 |
| sf-slack | <ajinkyaraghuwanshi> Yes thank you it ran but I am having some errors can you please look: | 13:46 |
| sf-slack | <ajinkyaraghuwanshi> ```Vivado% opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236' Running DRC as a precondition to command opt_design Starting DRC Task Command: report_drc (run_mandatory_drcs) for: opt_checks INFO: [DRC 23-27] Running DRC with 8 threads ERROR: [DRC INBB-3] Black | 13:46 |
| sf-slack | Box Instances: Cell 'inst1/$auto$simplemap.cc:517:simplemap_dlatch$103' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst1/$auto$simplemap.cc:517:simplemap_dlatch$104' of type | 13:46 |
| sf-slack | 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst1/$auto$simplemap.cc:517:simplemap_dlatch$105' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of | 13:46 |
| sf-slack | this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst1/$auto$simplemap.cc:517:simplemap_dlatch$106' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell | 13:46 |
| sf-slack | 'inst1/$auto$simplemap.cc:517:simplemap_dlatch$107' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst1/sum1' of type 'inst2/sum1/DSP48E1' has undefined contents and is considered a black box. The contents of this cell must be | 13:46 |
| sf-slack | defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$103' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell | 13:46 |
| sf-slack | 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$104' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$105' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has | 13:46 |
| sf-slack | undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$106' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. | 13:46 |
| sf-slack | ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107' of type 'inst2/$auto$simplemap.cc:517:simplemap_dlatch$107/$_DLATCH_P_' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. ERROR: [DRC INBB-3] Black Box Instances: Cell 'inst2/sum1' of type 'inst2/sum1/DSP48E1' has undefined contents and is considered a | 13:46 |
| sf-slack | black box. The contents of this cell must be defined for opt_design to complete successfully. report_drc (run_mandatory_drcs) completed successfully INFO: [Project 1-461] DRC finished with 12 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2002.320 | 13:46 |
| sf-slack | ; gain = 73.031 ; free physical = 133 ; free virtual = 20051 4 Infos, 0 Warnings, 0 Critical Warnings and 13 Errors encountered. opt_design failed ERROR: [Common 17-39] 'opt_design' failed due to earlier errors. Vivado% ``` | 13:46 |
| sf-slack | <ajinkyaraghuwanshi> Can anyone help me remove this error? | 14:03 |
| sf-slack | <mkurc> Hi @ajinkyaraghuwanshi It looks like the netlist from Yosys you have contains cells not recognized by Vivado | 14:09 |
| sf-slack | <mkurc> Can you paste Yosys commands that you have used for synthesis? | 14:10 |
| sf-slack | <ajinkyaraghuwanshi> ```read_verilog , synth_xilinx , write_edif adder.edf ``` | 14:16 |
| sf-slack | <ajinkyaraghuwanshi> adder.edf is the name of file | 14:17 |
| sf-slack | <ajinkyaraghuwanshi> these were the commands | 14:17 |
| sf-slack | <mkurc> Try synthesis and EDIF writing in a single pass plus add some options to synth_xilinx. I'd try: | 14:20 |
| sf-slack | <mkurc> `synth_xilinx -flatten -family xc7 -edif adder.edf` | 14:20 |
| sf-slack | <mkurc> after that you may run `stat` and see if there are any `$_DLATCH_P` cells reported. There shouldn't be any | 14:21 |
| sf-slack | <ajinkyaraghuwanshi> Yes there are `$_DLATCH_P` how should I remove them | 14:27 |
| sf-slack | <ajinkyaraghuwanshi> Precisely 10 latches | 14:28 |
| sf-slack | <mkurc> Hmm, it looks like a Yosys bug - those latches should get mapped to cells understandable by Vivado | 14:31 |
| tpb | <gatecat> modern Yosys should be mapping them, I think | 14:31 |
| tpb | <gatecat> what Yosys version are you using? | 14:32 |
| tpb | <gatecat> also, I'm slightly surprised that you've ended up with latches at all, it's fairly rare for latches to be intended in modern FPGA designs | 14:33 |
| sf-slack | <anuragmuttur123> Hello, I'm currently running the Picosoc example. I generated it on Symbiflow and that was successful. I'm now using fasm2bels to obtain the logical netlists. I do have a problem with the BRAM portion of it in the picosoc. I get this error: `ERROR: [DRC PDIL-1] Invalid Site Configuration: Invalid configuration for site RAMB18_X0Y26. Reason: Illegal pin placement. Cell pin 'RSTRAMARSTRAM' should map to element pin | 18:25 |
| sf-slack | 'RSTRAMARSTRAM' based on logical attributes. The nets do not match, even after accounting for possible logical pin inversion.Logical net: GLOBAL_LOGIC1` `Bel net: GLOBAL_LOGIC0, Illegal pin placement. Cell pin 'RSTRAMB' should map to element pin 'RSTRAMB' based on logical attributes. The nets do not match, even after accounting for possible logical pin inversion.Logical net: GLOBAL_LOGIC1` `Bel net: GLOBAL_LOGIC0, Illegal pin placement. | 18:25 |
| sf-slack | Cell pin 'RSTREGARSTREG' should map to element pin 'RSTREGARSTREG' based on logical attributes. The nets do not match, even after accounting for possible logical pin inversion.Logical net: GLOBAL_LOGIC1` `Bel net: GLOBAL_LOGIC0, Illegal pin placement. Cell pin 'RSTREGB' should map to element pin 'RSTREGB' based on logical attributes. The nets do not match, even after accounting for possible logical pin inversion.Logical net: GLOBAL_LOGIC1` | 18:25 |
| sf-slack | `Bel net: GLOBAL_LOGIC0`. When I use Vivado and look at the diagram, the following pins in which the errors are found is connected to Ground. But in the DCP file generated by Symbiflow that I observe, they are connected to VCC. I looked a little more into this and turns out that this happens during the conversion of fasm2bels. Is there a fix for this, or can this be fixed soon? Let me know if more information is needed. | 18:25 |
| sf-slack | <anuragmuttur123> This is for the arty 35 board | 18:28 |
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| -_whitenotifier-f666- [fpga-tool-perf] mithro opened issue #330: Provide lots of links to dashboards to make it easy to see the current state of things - https://git.io/Jc9g8 | 23:14 | |
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