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| sf-slack | <acomodi> @rodrigomelo9 ping (regarding the PyFPGA CLI) | 08:40 |
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| sf-slack | <rodrigomelo9> Hi @acomodi here I am, let me know any doubt. I am working in a branch: the specification of Verilog Includes and Defines, VHDL architectures and Parameters/Generics. | 11:13 |
| sf-slack | <acomodi> Hi, @rodrigomelo9, as far as I understand the idea would be to have a CLI to invoke EDA tools, and have symbiflow as part of this as well, correct? | 11:22 |
| sf-slack | <acomodi> In this scope, there have been thoughts to move the toolchain wrappers into something less platform-dependant and in general easier to maintain, so I think that their re-adaptation in python would be ideal in this case | 11:25 |
| sf-slack | <rodrigomelo9> This is the idea in the case of PyFPGA (https://github.com/PyFPGA/pyfpga). However, SymbiFlow (https://github.com/SymbiFlow/symbiflow-arch-defs/tree/master/xc/xc7/toolchain_wrappers) only supports xc, and I want to support as much FOSS as possible :) so I created OpenFlow (https://github.com/PyFPGA/openflow). | 11:26 |
| tpb | <https://x0.no/4uy20> (at github.com) | 11:26 |
| sf-slack | <rodrigomelo9> > In this scope, there have been thoughts to move the toolchain wrappers into something less platform-dependant and in general easier to maintain Mitro told me the same, and it was the reason to work in SymbiFlow CLI instead. | 11:28 |
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| sf-slack | <rodrigomelo9> SymbiFlow CLI (https://github.com/PyFPGA/symbiflow_cli) is a PoC, a starting point, which of course, can be renamed, modified, adapted, expanded, etc. | 11:31 |
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| sf-slack | <acomodi> Sounds good. One important point would be to enable support for different tools in the open flow such as yosys+VPR or yosys+nextpnr. For instance, the synthesis step when using VPR (at least for xc7) will require some additional steps as defined in the toolchain wrappers, which, at this point, will become part of the CLI | 11:46 |
| -_whitenotifier-2- [python-fpga-interchange] mtdudek opened issue #95: Why get_primitive_library is using self.strs - https://git.io/JnJZx | 11:48 | |
| sf-slack | <rodrigomelo9> Yes, I know (about the additional steps for XC7 and VPR). I started with ice40 and ecp5 because that is what I had from PyFPGA. | 11:50 |
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| sf-slack | <kgugala> Alse we have QuickLogic toolchain merged into SymbiFlow (the one for qlf FPGAs) | 11:51 |
| sf-slack | <rodrigomelo9> My first approach to select which tools to employ is to guess it based on the device part name. So, if it is an ice40 or ecp5, it will use nextpnr, but in the case of a Xilinx device, it will use VPR. Of course, we can add something to change this default behaviour, for advanced uses (for example, specify nextpnr for Xilinx devices?). | 11:52 |
| sf-slack | <rodrigomelo9> Hi @kgugala. Yes I know. I have not previous experience with QuickLogic devices, but I want to have :) so more than happy adding them. | 11:54 |
| sf-slack | <rodrigomelo9> I have a DE10 nano from Intel/Altera here, so I also want to add support for prjmistral, and others such as apicula, etc. | 11:55 |
| sf-slack | <rodrigomelo9> I guess, to add Xilinx and QuickLogic support to SymbiFlow CLI could be a good next step? | 11:57 |
| sf-slack | <kgugala> TBH those flows are pretty similar | 11:58 |
| sf-slack | <kgugala> IMO it should be fairly easy to make sth like SymbiFlow commot | 11:58 |
| sf-slack | <kgugala> *common | 11:58 |
| sf-slack | <kgugala> and just provide settings depending on targeted vendor/family | 11:59 |
| sf-slack | <rodrigomelo9> Yes, in case of iCE40 and ECP5, I am using something such as: ```{command} -Q {module} -p ' {options}; synth_{family} -top {top} -json {outdir}/{project}.json '``` | 12:07 |
| sf-slack | <rodrigomelo9> I don't know in the case of QuickLogic, but I saw that for Xilinx a huge Tcl is used | 12:08 |
| sf-slack | <rodrigomelo9> Well, I will add support for VPR, Xilinx and QuickLogic, based on the SymbiFlow's toolchain_wrappers | 12:21 |
| sf-slack | <rodrigomelo9> Please, feel free to open issues to discuss changes, new features, provide suggestions, etc. | 12:23 |
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| -_whitenotifier-2- [symbiflow-examples] WhiteNinjaZ opened issue #153: Error from instantiating MMCME2_BASE primitive - https://git.io/JnTNp | 17:46 | |
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| sf-slack | <josh.johnson.hire> (Reposting because this got buried in bot messages over the weekend) | 21:05 |
| sf-slack | <josh.johnson.hire> Hello everyone! Hope this is the right channel. I would love to find a way to contribute to this project. I've got decent experience with FPGA design, but only recently finished my E.E. degree so I'm still inexperienced. I'm pretty good with Verilog and C, and am learning Python now. If anyone knows who I should contact to get involved, let me know! Thanks everyone. | 21:05 |
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