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| mithro | Testing.... | 01:39 |
|---|---|---|
| cr1901_modern | Making a bridge? | 01:42 |
| mithro | Testing | 01:43 |
| sf-slack | <ept> @mithro Thank you very much! | 01:45 |
| mithro | Testing | 01:50 |
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| mithro | relay join | 02:22 |
| mithro | ~relay join | 02:22 |
| tpb | mithro: The operation succeeded. | 02:22 |
| mithro | @relay join | 02:23 |
| mithro | ~help | 02:23 |
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| tpb | <tansell> I probably don't know when to quit.... | 02:37 |
| tpb | <tansell> The Relay plugin doesn't like me apparently :-( | 02:39 |
| mithro | Or maybe it does now? | 02:39 |
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| cr1901_modern | Plugin seems to be working now? | 03:04 |
| tpb | <cr1901> At least, seems to be | 03:06 |
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| tpb | <emilazy> is this channel, uh, registered yet? :) | 06:52 |
| tpb | <lambda> /cs info says no :) | 07:07 |
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| sf-slack | <hadirkhan10> Hello guys, I am building an SoC generated from Chisel. I am using MMCM through clocking wizard in Vivado to create a clock of 8MHz. I want to build the buildstream through Symbiflow but the clocking wizard utilizes a module MMCME2_ADV which is Xilinx's closed IP. Any other way to use the PLL for my design and map it to the Arty A7 board? | 11:08 |
| sf-slack | <kgugala> hi @hadirkhan10 MMCME2_ADV is not a closed IP. It is a primitive available i 7 series FPGAs. It is supported in Symbiflow - you can simply instantiate it in your design | 11:11 |
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| sf-slack | <hadirkhan10> @kgugala I got an error. Something like `module definition for MMCME2_ADV not found` I will share the error when I'll re-run it | 12:02 |
| sf-slack | <kgugala> you can always try replacing MMCME2_ADV with PLLE2_ADV | 12:08 |
| sf-slack | <hadirkhan10> Oh.. let me see | 12:14 |
| sf-slack | <hadirkhan10> @kgugala to be precise I used the clocking wizard to generate a clock using MMCM option. It created two files. 1) just a wrapper 2) filename: clk_wiz_0_clk_wiz.v instantiates the MMCME2_ADV When replacing the MMCME2_ADV module in the file PLLE2_ADV I am getting the following error: ERROR: Module `PLLE2_ADV' referenced in module `clk_wiz_0_clk_wiz' in cell `mmcm_adv_inst' does not have a port named 'CLKFBSTOPPED'. | 12:30 |
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| sf-slack | <kgugala> PLLE does not have this port | 13:19 |
| sf-slack | <kgugala> If you really want to use clk wizzard I believe you can tell it to use PLLE instead of MMCM | 13:20 |
| sf-slack | <kgugala> I'd suggest instantiating those by hand | 13:20 |
| sf-slack | <kgugala> those are not complicated and it's way easier to maitain the project if you do it mnually | 13:20 |
| sf-slack | <kgugala> see https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf (page 70) | 13:21 |
| tpb | <https://x0.no/4uwoj> (at www.xilinx.com) | 13:21 |
| sf-slack | <kgugala> you can find there PLLE ports description (+ some info how this primitive works) | 13:22 |
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| sf-slack | <hadirkhan10> @kgugala thanks, let me look into it :) | 13:50 |
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| sf-slack | <vastarparaakshar> We are stuck at post-timing implementation simluation | 16:31 |
| sf-slack | <vastarparaakshar> We almost got everything right, but we are having problem with primitives.v for tb.do | 16:31 |
| sf-slack | <vastarparaakshar> so for primitives.v we need to manually find out blocks and add it on the file or we just need to attach some generated files already? | 16:32 |
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| tpb | <cr1901> mithro: Did you put in a registration to Libera yet for this project? | 20:54 |
| tpb | <cr1901> Asking b/c, well, no one has ops and the channel isn't registered yet | 20:54 |
| tpb | <emilazy> starting to think it may be best to ping mithro over a non-IRC communications medium :p | 21:14 |
| tpb | <mithro> I have sent the email | 21:14 |
| tpb | <cr1901> emilazy: Nah, mithro's historically good w/ getting back to me. These are exceptional times | 21:17 |
| -_whitenotifier-2- [symbiflow-examples] WhiteNinjaZ opened issue #151: Do incorrectly writen XDC files generate errors from the toolchain? - https://git.io/JGKg7 | 21:31 | |
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