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| mithro | @acomodi: Can you mark which of the pathways are supported by edalize and which are tested in https://docs.google.com/drawings/d/12SjkmrsoI-Me4feKJoUV5F_0cfH75AoWoEqyvfI2Uuw/edit before the meeting today? | 14:30 |
|---|---|---|
| tpb | Title: FPGA Interchange Testing Flow - Google Zeichnungen (at docs.google.com) | 14:30 |
| sf-slack1 | <acomodi> mithro: sure, will do now | 14:31 |
| mithro | @gatecat Is there a MUXF8 used in the RAM64E macro? | 14:57 |
| gatecat | mithro: RAM64E doesn't exist. RAMD64E is a leaf primitive representing a single RAM LUT, not a macro | 15:06 |
| gatecat | mithro: something like RAM256X1S (7-series) would include a MUXF8 in its expansion | 15:06 |
| gatecat | there's also RAM256X1D for UltraScale that also includes a MUXF8 in its expansion | 15:07 |
| mithro | @gatecat I'm just drawing my own examples at https://docs.google.com/document/d/1-0RF7cuNoZl2t0McTYgoXyxXa_8Tqu3JFw9ZL7bLF-I/edit# ? | 15:08 |
| tpb | Title: FPGA Interchange macros & chains - Google Docs (at docs.google.com) | 15:08 |
| mithro | RAM128X1D -- Oh - that is a dual port memory? | 15:08 |
| gatecat | mithro: yeah RAM128XD has two outputs, one is a read write port and the other is a read port only | 15:09 |
| gatecat | so there is no MUXF8, the outputs come from the two MUXF7s | 15:10 |
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| mithro | @gatecat I'm pretty sure my connections on the RAM128X1D diagram are wrong, But not quite sure how to fix them.... | 15:21 |
| gatecat | mithro: hang on, I'm afk now but I'll have a go at fixing it for you later | 15:29 |
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| gatecat | sorry, got tired of fighting google docs, let me work on a proper diagram | 16:14 |
| gatecat | it might be tomorrow now | 16:14 |
| cr1901_modern | Oh, did they start the transition to canvas already? | 16:14 |
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| mithro | acomodi: I'm not sure your updates are correct to the FPGA Interchange Testing Flow are correct? | 16:23 |
| mithro | acomodi: I'm pretty sure we don't have any tests running post synthesis simulation using a text bench? | 16:24 |
| sf-slack1 | <acomodi> mithro: we do actually. The same testbench is used for all three netlists | 16:25 |
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| sf-slack1 | <acomodi> mithro: https://github.com/SymbiFlow/fpga-interchange-tests/blob/0dcffe28969010e288256d770b7414e0cf7e615a/tests/tests.cmake#L142-L162 | 16:27 |
| mithro | acomodi: I don't see any output on https://source.cloud.google.com/results/invocations/2e65ab2f-aabf-4e2c-8ca8-fed0c6408cd8/targets/foss-fpga-tools%2Ffpga-interchange-tests%2Fpresubmit/log which would indicate it ran? | 16:27 |
| mithro | acomodi: Well awesome! | 16:28 |
| mithro | acomodi: Can we add the target names to the diagram? | 16:28 |
| sf-slack1 | <acomodi> mithro: sure | 16:28 |
| gatecat | mithro: this is how I think it should look | 16:30 |
| gatecat | https://usercontent.irccloud-cdn.com/file/iBZ2aIqS/Screenshot%20from%202021-05-13%2017-29-51.png | 16:30 |
| gatecat | will pick this up properly tomorrow though | 16:30 |
| gatecat | oops sorry some of the lines aren't quite right | 16:30 |
| gatecat | SVG version: https://usercontent.irccloud-cdn.com/file/8nlGI3q9/ramd128x1.svg | 16:34 |
| mithro | gatecat: I didn't realize the LUT itself was dual port... | 17:10 |
| gatecat | mithro: yeah, the write address is fed to all the LUTs in the tile from the inputs to the topmost LUT | 17:11 |
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