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| CarlosEDP | Hi all, I'm building a Docker container with Symbiflow focusing portability... while it builds the Arty demo fine, it couldn't find an instance of PLL2_BASE IP I use on my design. | 12:32 |
|---|---|---|
| CarlosEDP | It was generated on Vivado Clocking Wizard... | 12:32 |
| sf-slack | <kgugala> hi CarlosEDP | 12:33 |
| CarlosEDP | Hey Karol! :) | 12:33 |
| sf-slack | <kgugala> I think PPL2_ADV isi supported | 12:33 |
| CarlosEDP | ah ok.. let me check and swap them | 12:33 |
| CarlosEDP | another question, the toolchain didnt support my constraints in the format of -dict... | 12:34 |
| CarlosEDP | like | 12:34 |
| sf-slack | <kgugala> in xdc? | 12:34 |
| CarlosEDP | `set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clock }];` | 12:34 |
| CarlosEDP | yep | 12:34 |
| CarlosEDP | I had to break in two lines | 12:34 |
| sf-slack | <kgugala> I suppose this is a xdc yosys plugin limitation | 12:35 |
| * CarlosEDP < https://matrix.org/_matrix/media/r0/download/matrix.org/XmtgnwVAOZiwOdeoRGvghbGi/message.txt > | 12:35 | |
| sf-slack | <kgugala> @tmichalak can you look at this? | 12:35 |
| CarlosEDP | want me to open an issue? | 12:35 |
| sf-slack | <kgugala> yes, please | 12:35 |
| CarlosEDP | on which repo? symbiflow-arch-defs ? | 12:36 |
| sf-slack | <tmichalak> I believe there is an issue for this already | 12:36 |
| sf-slack | <tmichalak> I mean this is a missing feature | 12:36 |
| sf-slack | <tmichalak> but let me double check | 12:36 |
| CarlosEDP | also should I open an issue about the missing PLL2_BASE? | 12:37 |
| sf-slack | <kgugala> yep, this should be fairly easy to fix (I suppose) | 12:37 |
| sf-slack | <kgugala> It's just a missing techmap | 12:37 |
| sf-slack | <tmichalak> the issue with XDC is here: https://github.com/SymbiFlow/yosys-symbiflow-plugins/issues/32 | 12:39 |
| CarlosEDP | I found this about the PLL but doesn't seem the same thing | 12:40 |
| CarlosEDP | https://github.com/SymbiFlow/symbiflow-arch-defs/pull/2007 | 12:40 |
| sf-slack | <kgugala> so @mkurc can tell us more about it :) | 12:41 |
| -_whitenotifier-5- [symbiflow-arch-defs] carlosedp opened issue #2123: VPR error when using PLLE2_BASE in a design - https://git.io/JOnND | 12:45 | |
| CarlosEDP | aha, we have a whistleblower bot in the channel :D | 12:45 |
| sf-slack | <mkurc> So this PR you've linked adds the techmap for PLL_BASE | 12:48 |
| sf-slack | <mkurc> It transform PLL_BASE to PLL_ADV as the vendor tools do. | 12:48 |
| CarlosEDP | ah ok.. got it | 12:48 |
| sf-slack | <kgugala> we could potencially rebase this and merge? | 12:48 |
| sf-slack | <mkurc> Sure, let me look into that | 12:49 |
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| CarlosEDP | should `conda env create` also pip install the required packages? | 13:39 |
| CarlosEDP | because I'm getting the modules not found error running here | 13:39 |
| CarlosEDP | I had to `pip3 install -r ./${FPGA_FAM}/requirements.txt` manually | 13:39 |
| CarlosEDP | I'm doing this on a Docker container so It might be confusing the Python installs | 13:40 |
| CarlosEDP | this is my install flow: https://gist.github.com/carlosedp/1f9119e0645e842e474ec1a67b5aed7e | 13:41 |
| sf-slack | <kgugala> it should install them | 13:45 |
| sf-slack | <kgugala> maybe you need to set PYTHON_PATH? | 13:45 |
| CarlosEDP | humm.. maybe.. | 13:45 |
| sf-slack | <mkurc> `conda env create` doesn't do that on its own. In symbiflow you run `make env` which creates the env and install pip packages. | 13:47 |
| CarlosEDP | ah ok... well, I added the pip install step in my Dockerfile | 13:49 |
| mithro | CarlosEDP: morning! | 13:59 |
| CarlosEDP | Hi Tim! Morning | 13:59 |
| CarlosEDP | I'm already poking some stuff... and bugging the folks around here :) | 13:59 |
| mithro | CarlosEDP: As I mentioned, there is still a lot of work to polish the Xilinx flow | 14:19 |
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| -_whitenotifier-5- [actions] acomodi opened issue #17: Third party dir not excluded by license check - https://git.io/JOcC1 | 15:14 | |
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| mithro | CarlosEDP: In *theory*, you should be able to just build Yosys+yosys_symbiflow_plugins+VPR+prjxray-tools and then use the datafiles compiled from symbiflow-arch-defs rather than using conda directly. | 15:15 |
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| CarlosEDP | Yep! Right now I'm doing the default install but my idea is that.. | 15:21 |
| CarlosEDP | since the container doesn't need examples and etc | 15:21 |
| CarlosEDP | Just updated the Dockerfile, works fine now. I was able to build my test project and program it to the Arty with Vivado. | 15:27 |
| CarlosEDP | https://gist.github.com/carlosedp/1f9119e0645e842e474ec1a67b5aed7e | 15:27 |
| CarlosEDP | Gonna try to build xc3sprog natively on Mac now so I don't depend on a VM | 15:27 |
| * CarlosEDP < https://matrix.org/_matrix/media/r0/download/matrix.org/oISiXsYeQXoncHZvTMKtoduW/message.txt > | 15:28 | |
| CarlosEDP | Is it a known/expected error ? | 15:29 |
| sf-slack | <kgugala> CarlosEDP: you can also program those boardswith openOCD | 15:29 |
| sf-slack | <kgugala> CarlosEDP - it's not really an error (however it looks like so) | 15:29 |
| CarlosEDP | kgugala: | 15:30 |
| CarlosEDP | great... gonna try with it too | 15:30 |
| sf-slack | <kgugala> it's more like info message saying that bitstream writer will not use antlr (faster implementation) and it's falling bach to slower (pure python based) | 15:31 |
| CarlosEDP | yep.. thought it "should" work with the default antlr... and it didn't for some error | 15:31 |
| CarlosEDP | and it works! | 15:41 |
| CarlosEDP | ``` | 15:41 |
| CarlosEDP | openocd -f digilent-hs1.cfg -f xilinx-xc7.cfg -c "transport select jtag;init; pld load 0 /Users/cdepaula/projects/fusesoc/symbiflow/build/carlosedp_demo_chiselblinky_0/artya7-35t-oss-symbiflow/Toplevel.bit; exit" | 15:41 |
| CarlosEDP | ``` | 15:41 |
| CarlosEDP | Full opensource without VMs, Windows, Vivado... | 15:41 |
| sf-slack | <kgugala> YaaaY!! | 15:41 |
| sf-slack | <kgugala> now - time to open source the chip itself ;) | 15:42 |
| CarlosEDP | now, run it on FuseSoc ;) | 15:42 |
| CarlosEDP | with containers | 15:42 |
| CarlosEDP | except openocd part since on Mac/Windows you can't do USB passthru from plugged devices to the container... we were discussing this on Twitter other day | 15:43 |
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| CarlosEDP | there is only one "issue" with Symbiflow on a container... the size | 15:59 |
| * CarlosEDP < https://matrix.org/_matrix/media/r0/download/matrix.org/HHztnLlCGqMCQZIgrhIAqRFU/message.txt > | 15:59 | |
| sf-slack | <acomodi> CarlosEDP: I suppose this is because the container has all of the architectures in there (200T 100T z010 and 50T) | 16:00 |
| sf-slack | <kgugala> you don't really need all the devices definitions | 16:00 |
| * CarlosEDP < https://matrix.org/_matrix/media/r0/download/matrix.org/uejjULKninsTCVxPQSbTDAmt/message.txt > | 16:00 | |
| sf-slack | <acomodi> If you are interested in only the arty, the xc7a50t is enough | 16:01 |
| sf-slack | <acomodi> (unless is the 100T arty version) | 16:02 |
| mithro | CarlosEDP: How good is your C++? Those files compress *really* well, it would be awesome to see if there was much of a performance impact from reading a compressed version. | 16:07 |
| mithro | CarlosEDP: But so far it has generally been cheaper for me to send people hard drives then spend the developer time on that :-) | 16:08 |
| -_whitenotifier-5- [sphinx_symbiflow_theme] mithro opened issue #7: Migrate all the projects to the new sphinx theme - https://git.io/JOczm | 16:10 | |
| mithro | daniellimws: FWIW - https://github.com/orgs/SymbiFlow/projects/23 | 16:11 |
| CarlosEDP | sorry, was out for lunch :) | 16:35 |
| CarlosEDP | <mithro "Carlos Eduardo de Paula: How goo"> it's close to none... I haven't coded for real in C++ | 16:35 |
| CarlosEDP | ahd yes, they compress to like 20% original size with bz2 | 16:36 |
| CarlosEDP | one naive question... why these. "databases" are so much larger for Xilinx than for the Lattice devices? | 16:37 |
| mithro | CarlosEDP: A bunch of complicated reasons | 16:45 |
| mithro | CarlosEDP: I think even better is lmza or other.... | 16:45 |
| CarlosEDP | who reads them? VPR? | 16:46 |
| mithro | CarlosEDP: yes | 16:47 |
| mithro | CarlosEDP: VPR uses "flattened" databases | 16:47 |
| mithro | nextpnr uses flattened databases for ice40 and a more compressed format for the ecp5 | 17:06 |
| sf-slack | <cjearls> Several months ago, I received a recommendation to buy an OrangeCrab FPGA as a starter FPGA. I've really enjoyed trying it out, and I'm back looking for another recommendation. I have several hundred dollars to spend, and I'd like to purchase a larger FPGA, the OrangeCrab can only fit one Vexriscv core, and I'd like to be able to fit multiple. If possible, I'd like a board that works with the linux-on-litex project and | 17:22 |
| sf-slack | has an FPGA-accessible ethernet port and FPGA-accessible microSD card slot or SATA port. I'd like the board to have plenty of RAM for Linux. Also, I think I'm interested in working with HDMI or DisplayPort inputs and/or outputs in the future, so built-in FPGA-accessible ports for this and would be nice, or if not, PMODs or some other connector that can be adapted to display standards. Is there something like that with SymbiFlow | 17:22 |
| sf-slack | support? | 17:22 |
| sf-slack | <cjearls> Also, the more example files that are available for a board, whether open-source or through the manufacturer, the better | 17:22 |
| mithro | cjearls: The Arty A7-100T or the higher end Nexys Video boards are nice (non-open source boards) but the open source Xilinx tooling is a bit rougher | 17:43 |
| mithro | cjearls: Higher end ECP5 boards are still less common, Greg Davill's ButterStick is kind of interesting | 17:44 |
| CarlosEDP | ULX3S from Radiona is nice, there's a 85k LUT version and uses the full open-source toolchain | 17:45 |
| CarlosEDP | like your OrangeCrab | 17:45 |
| mithro | cjearls: What ECP5 variant of the OrangeCrab do you have? | 17:45 |
| CarlosEDP | But honestly as a beginner I found the Digilent boards amazing, in both quality and documentation | 17:46 |
| mithro | The Digilent boards are heavily used in education, it is one of the reason Xilinx is the dominate FPGA company because everyone learns with their boards.... | 17:47 |
| CarlosEDP | If you have the dough, this is a preeeery nice board with a beefy FPGA: https://store.digilentinc.com/genesys-2-kintex-7-fpga-development-board/ | 17:48 |
| tpb | Title: Xilinx Kintex-7 FPGA Development Board - Digilent (at store.digilentinc.com) | 17:48 |
| mithro | CarlosEDP: The "baby brother" of that board is https://store.digilentinc.com/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/ | 17:48 |
| tpb | Title: Nexys Video Artix-7 FPGA: Trainer Board for Multimedia Applications - Digilent (at store.digilentinc.com) | 17:48 |
| mithro | I would suggest the following order for Xilinx devices -- Arty A7-35T, Arty A7-100T, Nexys Video Artix-7, Genesys 2 Kintex-7 | 17:50 |
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| CarlosEDP | There it is, full containerized toolchain on a Mac | 18:20 |
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| CarlosEDP | using FuseSoc to build my Chisel project, run thru Symbiflow and program via openocd | 18:21 |
| CarlosEDP | https://asciinema.org/a/407503?speed=3 | 18:21 |
| tpb | Title: FPGA Bitstream for Xilinx Artix7 running on FuseSoc containers with open source toolchain - asciinema (at asciinema.org) | 18:21 |
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| sf-slack | <cjearls> I have the 25k LUT Orangecrab | 18:38 |
| zyp | did somebody suggest the ecpix-5 yet? | 18:40 |
| sf-slack | <cjearls> And I actually have a Genesys2 Kintex-7 on me currently, but I'm pretty sure the professor I'm working with is going to want it back once I graduate this semester :( | 18:41 |
| zyp | the ecpix-5 got both ethernet, microsd, sata, 512MB RAM, hdmi out, and 8 pmod sockets, so it seems like a good fit for your requirements | 18:45 |
| sf-slack | <cjearls> It looks like the ecpix-5 only has 256MB of RAM, otherwise, it's pretty tempting | 18:53 |
| sf-slack | <cjearls> Also the 85k LUT model is out of stock :S | 18:55 |
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| mithro | Oh yeah - the lambdaconcepts boards are pretty good! | 19:42 |
| mithro | cjearls: I might be tempted to send a Genesys2 Kintex-7 to a person who got it working well in SymbiFlow.... I've sent 2 people that board for other reasons before..... | 19:44 |
| mithro | CarlosEDP: will attest to the fact that doing cool things get you cool hardware :-) | 19:45 |
| CarlosEDP | yes it does! | 19:45 |
| sf-slack | <cjearls> What remains to be done to have it working well in SymbiFlow? It's something I'm absolutely interested in helping with | 19:45 |
| CarlosEDP | <mithro "cjearls: I might be tempted to s"> can I get in line? đ | 19:46 |
| sf-slack | <cjearls> As a heads-up, my thesis is due at the beginning of next month, after which I'll be moving across the country, so for the next couple weeks, I'm pretty slammed. Once I move, I'll have just under a month before I start my job that I'd love to spend helping improve Genesys2 Symbiflow support | 19:48 |
| mithro | The work to add support can be almost entirely done without needing the hardware | 19:51 |
| sf-slack | <cjearls> Oh, awesome | 19:52 |
| sf-slack | <cjearls> And to be fair, until I move, I have a Genesys2 on loan from my university | 19:52 |
| mithro | cjearls: The process of verification kind of looks like this -> https://docs.google.com/drawings/d/1NJlN-cPLNx4nULHiL4938RD-H14izpayqtNSQ4XRjfA/edit | 19:53 |
| tpb | Title: SymbiFlow Bitstream Verification Process - Google Zeichnungen (at docs.google.com) | 19:53 |
| sf-slack | <cjearls> I see. I have used Vivado briefly before, that seems like something I could do. Do the DRC and timing violation checks need to be implemented, or are there still bugs to work out, or something else? | 19:57 |
| mithro | cjearls: I think we don't know | 19:58 |
| mithro | cjearls: Also I think the biggest problem will be things like running out of memory and disk space and hence requiring other fixes before being able to move forward | 19:58 |
| sf-slack | <cjearls> Oh, ok, so that whole part of the bitstream verification is still to-do | 19:59 |
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| bjorkintosh | icestorm and symbiflow are not one and the same. | 20:01 |
| bjorkintosh | I don't know why I thought they were. | 20:01 |
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| sf-slack | <syed.ahmed.emails> Hello from syed to Tim | 20:03 |
| mithro | bjorkintosh: Well people confuse Linux + Debian and Linux + RedHat all the time | 20:03 |
| mithro | Hey syed | 20:03 |
| mithro | Take a look at https://twitter.com/unaimarcor/status/1382734443610304516 | 20:04 |
| bjorkintosh | right. makes sense. | 20:04 |
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| mithro | Syed: https://github.com/hdl/awesome/issues/98 | 20:07 |
| mithro | https://usercontent.irccloud-cdn.com/file/AGY9pdZF/image.png | 20:08 |
| mithro | Syed: It would be awesome to have https://github.com/google/verible in Visual Studio Code for linting and auto-formating your SystemVerilog code | 20:12 |
| sf-slack | <cjearls> So would the best way to start be to just choose an example project, and push it through Vivado and SymbiFlow, and compare the bitstreams? | 20:13 |
| mithro | Syed: https://cloud.google.com/blog/products/compute/scale-up-your-eda-flows-on-google-cloud | 20:14 |
| tpb | Title: A sample EDA design verification workflow on Google Cloud | Google Cloud Blog (at cloud.google.com) | 20:14 |
| mithro | Syed: It is an example of using SLURM to improve an EDA simulation workload | 20:15 |
| mithro | The âtile1_miniâ regression has 46 tests. Running all 46 tile1_mini tests sequentially took an average of 120 minutes. The parallel run for tile1_mini with 10 auto-scaled SLURM nodes completed in 21 minutesâa 6X improvement! | 20:15 |
| * mithro https://cloud.google.com/composer -- A Google Cloud Engineer said | 20:23 | |
| tpb | Title: Cloud Composer | Google Cloud (at cloud.google.com) | 20:23 |
| mithro | > Many customers use Composer because itâs âairflow under the hoodâ but we offset management / upgrades etc | 20:23 |
| mithro | https://airflow.apache.org/ | 20:24 |
| tpb | Title: Apache Airflow (at airflow.apache.org) | 20:24 |
| mithro | Syed: https://github.com/chriscardillo/gusty | 20:33 |
| mithro | Syed: https://cloud.google.com/ai-platform/training/docs/using-hyperparameter-tuning | 20:35 |
| tpb | Title: Using hyperparameter tuning | AI Platform Training | Google Cloud (at cloud.google.com) | 20:35 |
| mithro | Syed: https://cloud.google.com/ai-platform/optimizer/docs/overview | 20:36 |
| tpb | Title: Vizier overview | AI Platform Vizier | Google Cloud (at cloud.google.com) | 20:36 |
| mithro | CarlosEDP I would like to introduce you to Syed who is interested in helping edalize have support for distributed runners | 20:39 |
| mithro | Syed, I would like to introduce you to CarlosEDP who added the recent container support to EDALize | 20:39 |
| mithro | I should also note that umarcor is in this channel too | 20:40 |
| sf-slack | <syed.ahmed.emails> Hi CarlosEDP and Umarcor! | 20:40 |
| mithro | syed: you probably want to also join the https://gitter.im/hdl/community and https://gitter.im/librecores/fusesoc channels | 20:41 |
| tpb | Title: hdl/community - Gitter (at gitter.im) | 20:41 |
| mithro | Someone just pointed me to https://dmtn-025.lsst.io/ | 20:43 |
| tpb | Title: DMTN-025: A survey of workflow management systems (at dmtn-025.lsst.io) | 20:43 |
| mithro | Apparently olofk is hiding on the slack channel too! | 20:43 |
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| sf-slack | <olof.kindgren> Hi there | 20:44 |
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| sf-slack | <olof.kindgren> Haven't been here in a while | 20:47 |
| mithro | Syed: also look at https://github.com/verilog-to-routing/vtr-verilog-to-routing/tree/master/vtr_flow | 20:48 |
| mithro | Syed: https://docs.verilogtorouting.org/en/latest/vtr/running_vtr/ | 20:49 |
| tpb | Title: Running the VTR Flow Verilog-to-Routing 8.1.0-dev documentation (at docs.verilogtorouting.org) | 20:49 |
| sf-slack | <pgielda> @olof.kindgren too many channels ;) | 20:54 |
| sf-slack | <olof.kindgren> @pgielda Yeah. Although it's mostly just slighly different subsets of people in all of them :) | 20:56 |
| sf-slack | <pgielda> this makes it even harder | 21:00 |
| sf-slack | <pgielda> if it was a completely different set then it would be easier to track ;) | 21:00 |
| mithro | umarcor / Syed / CarlosEDP / olofk: Any idea what hammer / chipyard from Berkeley uses for this type of stuff? | 21:00 |
| sf-slack | <cjearls> Chipyard is AWS-based | 21:01 |
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| CarlosEDP | Sorry, was in a quick "solder PCB break" ... hehe.. yesterday I almost ripped out the micro usb connector from a PCB I was testing... just soldered it.. the flux arrived đ | 21:13 |
| CarlosEDP | Hi Syed! It's a pleasure | 21:14 |
| CarlosEDP | So Olof is around too... I'm on Matrix.. I don't see him | 21:14 |
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| umarcor | cjearls: since you asked last time, we added a list of boards to https://hdl.github.io/awesome/ Apart from the Arty, Nexys and others from Xilinx, you might like the ULX3S or the ECPIX-5. Both have variants with the ECP5 85F, which is larger than the one in the OrangeCrab (25F). | 21:31 |
| tpb | Title: Awesome HDL | Home (at hdl.github.io) | 21:31 |
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| umarcor | Given the requirements you mentioned, I would recoment PYNQ or other Zynq based boards from Xilinx/Digilent. They provide 1-2 ARM cores running at 500-900MHz, plus the programmable region (FPGA) in the same SoC. However, your are yet dependent on vendor tools if you want to use them. | 21:33 |
| umarcor | mithro: Digilent boards are not only used but also discounted in education. I got my PYNQ at $65. Not through my uni, but just using my uni e-mail on the Digilent site. | 21:35 |
| umarcor | oh, now I see that ECPIX was mentioned later... | 21:37 |
| umarcor | syed, mithro, with regard to Verible support in VSCode, see this dialogue: https://github.com/TerosTechnology/vscode-terosHDL/issues/99 | 21:45 |
| umarcor | suzizecat in gitter channel GHDL has a mixed-language synthesis example (VHDL, Verilog and System Verilog) and he is interested in havin mixed-language LSP support by combining Verible with GHDL and/or rust_hdl | 21:46 |
| sf-slack | <syed.ahmed.emails> thanks! | 21:47 |
| sf-slack | <syed.ahmed.emails> Tim and I were chatting that VSCode should become the default GUI for open source fpga toolchain :) | 21:50 |
| yeti | emacs! | 21:50 |
| yeti | :-P | 21:50 |
| sf-slack | <syed.ahmed.emails> hahah | 21:50 |
| umarcor | wrt being in this channel, I'm mostly always online, but I don't start the IRC client automatically. So, sometimes I might not see something. Ping me in gitter if you want to be sure. | 21:50 |
| sf-slack | <syed.ahmed.emails> I was hoping to annoy somebody with that | 21:50 |
| umarcor | syed, have a look at TerosHDL, the project from that last link | 21:51 |
| umarcor | https://terostechnology.github.io/terosHDLdoc/ | 21:51 |
| tpb | Title: Welcome to TerosHDLâs documentation! TerosHDL 0.1.4 documentation (at terostechnology.github.io) | 21:51 |
| umarcor | however, we know of people which use GHDL's LSP with VSCode, vim or emacs. Hence, any "multilanguage" LSP might work regardless of the editor. | 21:52 |
| umarcor | mithro: I'm not aware of hammer/chipyard... | 21:53 |
| umarcor | jokes aside, the remote containers or remote wsl features of VSCode are really nice; but not open source. | 21:54 |
| sf-slack | <syed.ahmed.emails> nice! TerosHDL looks nice, although got a little confused with the name if it were a new HDL | 21:54 |
| umarcor | yeah, I don't know were is the name coming from: https://www.terostech.com/ | 21:56 |
| tpb | Title: Teros Technology Develop hardware, take advantage of software tools (at www.terostech.com) | 21:56 |
| umarcor | despite the name, it's not a company AFAIAA, just a group of friends/colleagues | 21:57 |
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| sf-slack | <romckend> Hello, I work at BYU and we are using the python-fpga-interchange project as part of our bootcamp. We noticed that the DeviceResources python interface does not expose all of the constructs available in the capnp file generated by Rapid wright, and we are considering expanding it. Is there any specific reason why the python object structures do not have everything in the capnp file? | 22:14 |
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