Monday, 2021-03-22

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-_whitenotifier-4- [fasm] the-centry opened issue #66: If there someone could tell me how to install fasm in windows? - https://git.io/JmbkN04:00
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-_whitenotifier-4- [fpga-tool-perf] olofk opened issue #320: Adjust to changes in Edalize icetime invocation - https://git.io/JmNPQ13:15
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litghostmithro: LGTM for db update15:57
mithrolitghost: Database updated then16:02
mithrolitghost: BTW I have some updates to your rapidyaml python packaging pull request16:02
litghostFeel free to just push a new PR if you know how to fix the issues16:03
litghostJust grab my branch from my fork, etc16:03
litghostOr you could push a copy to a symbiflow-fork so we can both hack on it16:03
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sf-slack<nils.albartus>16:19
sf-slack<nils.albartus> Hey guys, I have a bitstream generated from Vivado for the zedboard. I tried to use the fasm2bel tool to get a netlist out of it. for some reason it crashed, because (and thats my best bet) when trying to recreate the routes it finds a pip of type hint, which I guess does not make sense. any idea how to fix this?16:19
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sf-slack<nils.albartus> i would be fine if the tool might give me some not complete netlist with some connections missing. is this error coming up due to an incomplete database?16:21
litghostPossible16:21
litghostfasm2bels can only really work on bitstreams that are complete16:21
sf-slack<nils.albartus> the bitstream is complete16:22
litghostIncomplete nets do prevent it from working, and that isn't that suprising16:22
litghostThe bitstream database is completely, e.g. the bitstream is completely understood16:22
sf-slack<nils.albartus> ah okay16:22
sf-slack<nils.albartus> so what do you suggest?16:22
litghostIf you look at the output, are there any "unknown" bits?16:22
sf-slack<nils.albartus> i sent you the entire output above16:23
litghostWe'll, first see if the output of "bit2fasm --verbose" reports any unknowns16:23
sf-slack<nils.albartus> okay16:23
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sf-slack<nils.albartus> ```# In frame 0x0042001a 6 bits were not converted. { unknown_bit = "0042001a_16_7", unknown_segment = "0x00420000", unknown_segbit = "26_519" } { unknown_bit = "0042001a_17_25", unknown_segment = "0x00420000", unknown_segbit = "26_569" } { unknown_bit = "0042001a_28_7", unknown_segment = "0x00420000", unknown_segbit = "26_903" } { unknown_bit = "0042001a_29_25", unknown_segment = "0x00420000", unknown_segbit =16:29
sf-slack"26_953" } { unknown_bit = "0042001a_97_7", unknown_segment = "0x00420000", unknown_segbit = "26_3111" } { unknown_bit = "0042001a_98_25", unknown_segment = "0x00420000", unknown_segbit = "26_3161" }  # In frame 0x0042001b 2 bits were not converted. { unknown_bit = "0042001b_59_6", unknown_segment = "0x00420000", unknown_segbit = "27_1894" } { unknown_bit = "0042001b_60_24", unknown_segment = "0x00420000", unknown_segbit =16:29
sf-slack"27_1944" }  # In frame 0x00420025 2 bits were not converted. { unknown_bit = "00420025_50_28", unknown_segment = "0x00420000", unknown_segbit = "37_1628" } { unknown_bit = "00420025_50_29", unknown_segment = "0x00420000", unknown_segbit = "37_1629" }```16:29
sf-slack<nils.albartus> this is what you mean i guess?16:29
sf-slack<nils.albartus> so i probably need to turn on the fuzzers? anyway to specifically target them to my missing bits?16:30
litghostYes16:34
litghostAnd yes16:34
litghostFirst step is to do a gross check to see "where" in the tile grid those bits are16:34
litghostE.g. which column / tile the bits likely are associated with16:34
litghostWe've recently documented more bits in the GTP, but those fuzzers only run on artix16:35
sf-slack<nils.albartus> alright how do i that? can i create a FASM file?16:35
litghostWe've also documented some more DSP bits16:35
litghostBe more specific?16:35
litghostYour second question doesn't really make sense16:35
sf-slack<nils.albartus> how to i do the “gross check”?16:36
litghostJust grep the tilegrid.json for your device16:36
sf-slack<nils.albartus> so maybe a few follow up questions: • the frame where my missing bits are i know from the bit2fasm tool. how can i find more information in my tilegrid.json (which is in xc7z020s) to actually figure out what is missing? what exactly am i looking for (or to rephrase the question: what am i supposed to “grep”)? from my understanding there are certain configuration for the pips missing in the database, is this16:55
sf-slackcorrect? • once i figure out which exact pip bits might be missing, what do i have to do next? i guess use the fuzzers to identify the missing bits in the database?16:55
litghostSo first off, they might be pips, they might not be16:57
litghostDon't assume16:57
litghostThe segment address is the frame address in tilegrid, and generally corrisponds to 1 column16:58
litghostTiles within a column are typically linearlly addressed16:58
litghostSo bits with low word offsets appear in tiles earlier than bits with high word offsets16:58
litghostSo between knowing which column of the grid the bits fell, and bounding the tile range based on the word offset, you can usually narrow down which tile the bits belong too16:59
litghostFrom there, it is a matter of either fixing or writing a fuzzer to document the remaining bits16:59
litghostAlternatively, if the bits belong to an optional feature (e.g. DSP or XADC), just remove those from your designs17:00
sf-slack<nils.albartus> alright. i will give this a shot tomorrow. thanks for the first initial push ;)17:02
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bryce_Hello! I was wondering if there was a source of information where I could go to get a broad overview of the functional status of the project, and in particular the xilinx reverse engineering effort. Something like a "state of the project" blog, so I can keep tabs on it without lurking here or following a bunch of other sources? The open source FPGA efforts are of great interest to me, but unfortunately I'm balancing my research interests17:10
bryce_with an early-stage medical career and I don't have as much time as I'd like to keep tabs on how this is going.17:10
bryce_TLDR - is there a place I can go to keep track of the progress of project xray, symbiflow etc without following a bunch of twitters or IRC channels, so I can know when the time is right to drop the $$ for a Xilinx dev board?17:11
litghosthttps://github.com/antmicro/symbiflow-examples is where we put our functional demos17:13
litghostSo for example, there is a linux capable SoC with DDR and ethernet up there17:13
litghostThat isn't precisely what you are asking for17:14
bryce_It isn't, but that's pretty helpful; I have enough technical background to have a broad sense of how hard various things are, so it helps to know what people have got working.17:14
bryce_So, thanks, that's useful at least.17:14
bryce_I'm really looking forward to seeing where FPGAs go when they're free of these awful proprietary development tools17:17
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bryce_On an unrelated note, I went to buy a dev board and saw this weird thing on ebay, obviously not a dev board: https://www.ebay.com/itm/284146993530  <- What the heck needs TEN Virtex-6 FPGAs but has no visible RAM or high-speed interfaces? Very strange, really curious what it could be for.18:24
tpbTitle: Qty:10 On Board Xilinx Virtex-6 XC6VLX130T | eBay (at www.ebay.com)18:24
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mithroThis looks super cool -> https://github.com/pypa/setuptools/issues/new/choose22:53
mithroLooks like we need https://github.com/pypa/setuptools/blob/main/.github/ISSUE_TEMPLATE/config.yml ...22:54
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mithrolitghost: Have you seen "ImportError: dynamic module does not define module export function (PyInit_ryml)"23:56
litghostNo23:57
litghostI assume it is what it says on the tin?23:57
litghostE.g. visibility rules only the SO mark it as not visible23:57
litghostWhat happens if you run "nm" or equiv?23:57

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