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| -_whitenotifier-5- [sv-tests] mithro opened issue #1346: Pull request "Compared test results" small feature requests - https://git.io/Jt1aJ | 16:31 | |
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| -_whitenotifier-5- [fasm] mithro opened issue #50: Remove `add_flags` method in setup.py by fixing cmake config file - https://git.io/Jt1iT | 18:10 | |
| -_whitenotifier-5- [fasm] mithro opened issue #51: Improve the cmake flag configuration - https://git.io/Jt1im | 18:13 | |
| -_whitenotifier-5- [fasm] mithro opened issue #52: Get the antlr / cython binaries building on Windows - https://git.io/Jt1ia | 18:18 | |
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| sf-slack4 | <sdamghan> Hi all, Is there anyway to specify .input and .output for a sub-circuit in Yosys BLIF output ? | 18:33 |
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| litghost | Can you rephrase your question? | 19:08 |
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| -_whitenotifier-5- [sv-tests] MikePopoloski opened issue #1347: Ibex core test passes verilator-specific files to other tools - https://git.io/Jt11K | 19:14 | |
| -_whitenotifier-5- [sv-tests] MikePopoloski opened issue #1348: SweRV core has possible syntax errors - https://git.io/Jt117 | 19:18 | |
| sf-slack4 | <sdamghan> Example: assign q = a + b After "proc; opt; memory; write_blif $PATH;" Yosys generates the following information for the add operation: .names $undef .subckt $add A=a B=b Y=q .end I'm wondering is it possible to generate the corresponding .model record for the above mentioned sub-circuit in Yosys, for instance something like this: | 19:25 |
| sf-slack4 | .model $undef .inputs A B | 19:25 |
| sf-slack4 | <litghost> FYI, the model in that case would be $add, not $undef | 19:43 |
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| litghost | It can and should do the right thing | 19:45 |
| sf-slack4 | <sdamghan> Yes, my bad. You are right. Anyway, is there any possibility? | 19:45 |
| litghost | It may be skipping $add because of https://github.com/YosysHQ/yosys/blob/78684596dcd6e5c62d020d13480ed6d081c865bd/backends/blif/blif.cc#L656-L657 | 19:46 |
| sf-slack4 | <sdamghan> Thank you! I have just checked, however, Yosys does not generate the *.model* record related to the sub-circuit in the BLIF file. I have checked for addition, multiplication and memory. it should be noted that I achieved the same results with and without *-blackbox* flag for write_blif. | 20:05 |
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| -_whitenotifier-5- [symbiflow-arch-defs] eljuligallego opened issue #2032: efinix FPGAs? - https://git.io/Jt19B | 20:52 | |
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| -_whitenotifier-5- [python-fpga-interchange] litghost opened issue #21: FPGA interchange logical netlist GND/VCC cell references should come from device database - https://git.io/Jt1N9 | 23:58 | |
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