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infinite_recursi | How to visualize the compiled code on hx8k ice40? Like the number of luts used, how much of logic is used, etc.? | 12:38 |
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Lofty | kgugala: Do you think it would be a good idea to modify the Symbiflow SDC plugin itself? I think that would help other ABC9 flows that use SDC files | 15:23 |
sf-slack | <kgugala> @Lofty: If you think modyfing it makes sense, please do (you can always open a PR to the plugins repo :)) | 15:25 |
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Lofty | kgugala: Made a PR to the SDC plugin; also pushed a commit to quicklogic-sta to assume a 12MHz clock if none specified | 16:26 |
Lofty | This should really reduce area for most of the small testcases :P | 16:27 |
sf-slack | <kgugala> thanks | 16:27 |
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-_whitenotifier- [yosys-symbiflow-plugins] mithro opened issue #76: Improve the README file - https://git.io/Jt0OA | 19:24 | |
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mithro | https://twitter.com/nextdayvideo/status/1355896718827479040 - #lca2021 - @nullobject - FPGA Design with Chisel | 20:24 |
mithro | https://twitter.com/nextdayvideo/status/1355865635910111236 - #lca2021 - @Bbff63565228 - Open Source FPGA Tooling, Our Journey from Resistance to Adoption | 20:25 |
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