Saturday, 2021-01-23

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lambdais it possible that the examples (xc7/counter_test for arty_35 in my case) require symbiflow's yosys fork? I'm hitting an assert in ABC9 with latest master upstream yosys07:50
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nickoelitghost: How do I run simulation on the counter_test?10:57
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nickoeWhy are there two implementations of the counter in https://github.com/SymbiFlow/symbiflow-examples/tree/master/xc7/counter_test ?  counter.v and counter_zynq.v?11:02
sf-slack<kgugala> nickoe: counter_zynq instantiates ps7 primitive and uses Zynq's hard CPU gpios to control the counter logic (enabling counter and changing count direction)11:06
nickoemm, ok11:09
nickoemm, why cna't I follow the links to the submodules here? I think one used to be able to do that in github, https://github.com/SymbiFlow/symbiflow-docs/tree/master/source11:36
sf-slack<kgugala> bacause they are defined with relative addresses see https://github.com/SymbiFlow/symbiflow-docs/blob/master/.gitmodules11:39
sf-slack<kgugala> apparently github cannot create links from relative gitmodules11:40
nickoeoh, but that is also a bit funky do to it like that?11:49
sf-slack<kgugala> with relative submodules it's easier to handle this in forks11:49
sf-slack<kgugala> this repo is for documentation and it combines info from submodules, so if you work on it you often have to change a few repos at once11:50
nickoemm, I see11:51
sf-slack<kgugala> with relative submodules you don't need to change the addresses11:51
nickoeDo you happen to know how I can run simulation on the symbiflow-examples?11:53
sf-slack<kgugala> this is a standard verilog code11:53
sf-slack<kgugala> you can use any verilog simulator to simulate this11:54
sf-slack<kgugala> e.g icarus or Verilator11:54
nickoemm, but how do I do that? I am not really familiar with icarus or verilator. I may have expected it to be a make option.11:56
sf-slack<kgugala> symbiflow-examples repo is to show how to use the FPGA toolchain to build designs and upload them into the FPGA chips11:59
nickoeI am reading https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html12:00
sf-slack<kgugala> cocotb is a great simulation environment https://docs.cocotb.org/en/stable/12:01
tpbTitle: Welcome to cocotb’s documentation! cocotb 1.4.0 documentation (at docs.cocotb.org)12:01
sf-slack<kgugala> you can desing your testbenches in python and simulate Verilog/SystemVerilog/VHDL designs using simulator you like12:02
sf-slack<kgugala> it can handle Verilator and icarus (and many others)12:02
nickoemmm, https://dpaste.com/5DHQBE6SZ kgugala Shouldn't this compile fine?12:27
tpbTitle: dpaste: 5DHQBE6SZ (at dpaste.com)12:27
nickoeor do I need to make something to contain it?12:28
sf-slack<kgugala> BUFG is an FPGA primitive12:36
sf-slack<kgugala> you need simulation model for it12:36
sf-slack<kgugala> you can use this one https://github.com/Xilinx/XilinxUnisimLibrary/blob/master/verilog/src/unisims/BUFG.v12:38
nickoemm, ok, I will try that in a moment, but in the meantime I tried to modify it with https://github.com/nickoe/symbiflow-examples/commit/277c5bb80fc1b37e2aaa82f02662f03833f86f48   but that fails to build with12:39
nickoeERROR: set_property IO_LOC_PAIRS: Incorrect number of arguments.12:39
nickoeohh, led vs LED?12:40
nickoeok, that certainly does not complain that early12:41
nickoeyay, the counter works on the board12:42
sf-slack<kgugala> yaay12:42
sf-slack<kgugala> what board do  you use>12:42
sf-slack<kgugala> ?12:42
nickoebasys312:44
sf-slack<kgugala> cool12:46
nickoekgugala, mm, how should I verilate it?12:46
nickoeI just tried to wget BUFG.v and do "verilator -Wall --trace -cc counter.v  BUFG.v"  but it errors12:47
nickoe%Error-TIMESCALEMOD: counter.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2)12:47
nickoemm, I guess I need to add that timescale ting?12:47
nickoeohh, no, it complains about bit widths12:48
nickoehttps://dpaste.com/7D583F5SZ12:48
tpbTitle: dpaste: 7D583F5SZ (at dpaste.com)12:48
sf-slack<kgugala> make left and right side equal width12:49
nickoeis genfasm single threaded?12:51
nickoealways, or is this just because I essentially only have on source file?12:51
sf-slack<kgugala> i think it is single threaded12:51
nickoeI see, the reg is larger to have a bigger counter reg, but I guess I just need to assigne the appropiate portion of the reg to the leds12:52
nickoeso I think it built it, but I gues I don't have a binary to run the simluation12:53
* nickoe goes reading that zipcpu post a bit further12:54
sf-slack<kgugala> once you verilate the design you get a C++ model of (a class) you also need some kind of a tesbench - another C++ piece of code where you instatiate the class with the mode, drive it inputs (optionally read oputputs) and push the simulation forward12:56
sf-slack<kgugala> you have to build it all together (just like any other C++ program) linking against Verilator's runtime and run12:57
nickoewell, right now I have nothing more that what you see in the branch12:57
nickoeI assume there is some boiler plate code I need to get13:05
sf-slack<kgugala> take a look at Verilator's docs https://www.veripool.org/wiki/verilator/Manual-verilator#EXAMPLE-C-EXECUTION13:07
tpbTitle: Manual-verilator - Verilator - Veripool (at www.veripool.org)13:07
nickoemmm, I don't seem to get a binary, let me commit13:13
nickoehttps://github.com/nickoe/symbiflow-examples/commit/48627c6488e0df0af785ad64bd218b4639b5611713:14
nickoeI try to do "verilator -Wall --trace --cc counter.v BUFG.v --exe --build sim_main.cpp"13:14
nickoeSo I am looking for a Vcounter binary in obj_dir, but none exist and I don't get errors with that command.13:15
nickoeor.. I guess I do, it exited becasue of a warning.13:15
nickoesigh, all this new syntax when used to read gcc errors, %Warning-DECLFILENAME: counter.v:3:8: Filename 'counter' does not match MODULE name: 'top'13:16
nickoeremoving -Wall it do build13:18
nickoea binary that runs forever seemingly.13:18
sf-slack<kgugala> this is what your code do - it runs i until finish is called in verilog13:19
sf-slack<kgugala> I assume your counter does not do that13:19
sf-slack<kgugala> also you may want to dump vcd13:20
sf-slack<kgugala> (so you can watch signal traces later)13:20
sf-slack<kgugala> e.g. with gdkwave13:20
nickoeyeah, that is what I want. Do I need to call dump vcd manually in sim_main.cpp?13:21
sf-slack<kgugala> look for "How do I generate waveforms (traces) in C++?" in https://www.veripool.org/wiki/verilator/Manual-verilator13:23
tpbTitle: Manual-verilator - Verilator - Veripool (at www.veripool.org)13:23
sf-slack<kgugala> it explains all the steps you need13:23
nickoemmm, is topp a type?13:27
nickoe*typo13:27
nickoeI guess it is to be the pointer here?   Vcounter* top = new Vcounter;13:29
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sf-slack<kgugala> I think Verialtor's examples may be heplful https://github.com/verilator/verilator/tree/master/examples13:33
sf-slack<kgugala> they have pretty deatailed commnents in the code13:33
nickoethank you, I will have a look -- but will get some fresh air in the meantime.13:49
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mithrodaveshah: https://docs.google.com/document/d/1o548m8mJnFTck2-i1A0sSXoe3VvL32irySqE5NBJvPY/edit#14:42
tpbTitle: nextpnr "Try Hard" mode - Google Docs (at docs.google.com)14:43
daveshahmithro: because of some issues like parallelism in the logging code, I'd recommend starting with a wrapper14:44
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mithrodaveshah: Okay, do you think that such a wrapper could be shipped with nextpnr? I'm thinking about people who are currently "locking the random seed" when they are doing PnR.14:51
daveshahYeah, I wouldn't have a problem with that14:52
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nickoekgugala can I access signals inside the module in the testbench?15:44
nickoewith verilator15:44
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nickoemmm, I think I made it simulate stuff, but for some reason it does not look like the output of the module with the led wires are changing16:18
nickoebut the counter is running fine16:18
nickoemmm16:30
nickoeI am not sure I understand why I get this error. All I modified was the counter assignment to the led and add   timescale for sim https://dpaste.com/EA5XXBHGA16:33
tpbTitle: dpaste: EA5XXBHGA (at dpaste.com)16:33
nickoeok16:44
nickoe-    assign led[3:0] = counter >> LOG2DELAY;16:44
nickoe+    assign led[3:0] = counter[3:0] >> LOG2DELAY;16:44
nickoeI guess it is that addition of that range that causes that16:44
nickoeok, that solved it for simulation and real, fixed with: assign led[15:0] = counter[BITS+LOG2DELAY-1:LOG2DELAY];16:59
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nickoeCan one initialize internal variables of a verilog module with verilator?21:35
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nickoeCan one install the symbiflow toolchaing for the upduino (ice40) with the symbiflow examples guide, or how does that work?22:35
nickoeor should I use make env from arch defs? I assume that "make env" from that essentially replaces the instructions on this page?  https://symbiflow-examples.readthedocs.io/en/latest/getting-symbiflow.html22:38
tpbTitle: Getting SymbiFlow SymbiFlow examples documentation (at symbiflow-examples.readthedocs.io)22:38
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