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| sf-slack | <mpictor> litghost, umarcor: thanks! | 03:29 |
|---|---|---|
| sf-slack | <mpictor> > If you are not modifying the arch-defs support, we recommend you use https://github.com/SymbiFlow/symbiflow-examples/ which pulls down the outputs of arch-defs. the getting started page on the site seemed to be directing me to arch-defs. didn't seem quite right but it was the best lead I had :) | 03:31 |
| sf-slack | <mpictor> maybe should change the docs to point to the examples repo | 03:31 |
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| Guest4447 | I am a beginner. I need some help. I have hx8k board from olimex and I intend to use flashrom utility on RPI3 with FreeBSD to program my fpga | 06:10 |
| Guest4447 | I also intend to use clash (haskell) for coding logic | 06:11 |
| Guest4447 | My question is, what do the steps look like? What is yosys, arachne-pnr and icestorm? | 06:11 |
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| sf-slack | <schris15> Hello, I'm interested in contributing to this project. I'm new to FPGAs. I have some basic knowledge of HDL languages and Docker. I'm have some experience with Python and C++. Where can I start contributing to the project? | 09:32 |
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| hansfbaier | sf-slack: Are you interested in Xilinx 7 series reveng? Here you can get started:https://symbiflow.readthedocs.io/projects/prjxray/en/latest/db_dev_process/readme.html | 10:28 |
| tpb | Title: Project X-Ray Project X-Ray 0.0-3318-g77e8b24c documentation (at symbiflow.readthedocs.io) | 10:28 |
| hansfbaier | sf-slack: See also the other nodes in the documentation page. That should keep you busy for some time... | 10:29 |
| hansfbaier | sf-slack: Also in the issue there are issues marked as ´good first issue´: https://github.com/SymbiFlow/prjxray/labels/good%20first%20issue | 10:31 |
| hansfbaier | sf-slack: This is all for Xilinx series 7 | 10:32 |
| hansfbaier | sf-slack: For Intel/Altera there is #prjmistral | 10:32 |
| hansfbaier | sf-slack: and for Lattice project trellis | 10:32 |
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| infinite_recursi | Hello, I'm a beginner in FPGA. I have an Olimex HX8K which I wish to program using flashrom utility in RPI3 with FreeBSD. I need some help. | 12:32 |
| infinite_recursi | Can someone help me with the basic steps on how FPGA programming is done. I intend to write code in clash (haskell), get hdl code, and then somehow use yosys, arachne-pnr and icestorm. | 12:33 |
| infinite_recursi | However, I have no idea what yosys, arachne and icestorm do! Can someone please explain in simple words to me these processes? Thanks in advance! | 12:34 |
| lambda | infinite_recursi: first of all, you probably want nextpnr, arachne-pnr's successor | 12:43 |
| infinite_recursi | ok, I'll see nextpnr. But why? | 12:45 |
| lambda | arachne-pnr is deprecated and not maintained anymore | 12:46 |
| infinite_recursi | I get how gcc converts C code to CPU instructions, etc. What are we doing here going from hdl to bitstream I presume at the end?! | 12:47 |
| sf-slack | <pgielda> @hansfbaier, sf-slack is a gateway bot that is forwarding messages from slack not a real username. | 12:47 |
| sf-slack | <pgielda> (just FYI) | 12:47 |
| lambda | infinite_recursi: yosys does the synthesis, i.e. converting your HDL to a netlist (circuit) of FPGA components (LUTs, flipflops, RAM blocks, ...), then nextpnr places these components into a concrete model of the specific FPGA you're using and routes the connections between them | 12:49 |
| infinite_recursi | got it and icestorm? | 12:51 |
| infinite_recursi | So do we have to control parameters of these compilation steps or is this automatic? Like as FPGA programmers, do we have to worry about internal things of these 3 softwares? | 12:52 |
| infinite_recursi | Like setting config params? | 12:53 |
| lambda | infinite_recursi: icestorm is the project that reverse-engineered iCE40 FPGAs, resulting in both the model (chipdb) used by nextpnr as well as a collection of tools to create bitstreams, etc | 12:53 |
| lambda | infinite_recursi: not really, for simple projects all you have to configure is the FPGA you want to build for | 12:53 |
| lambda | e.g. use `synth_ice40` in yosys, and run nextpnr-ice40 --hx8k with the correct --package | 12:54 |
| infinite_recursi | Noted. And where to find standard projects where I can build on top of others' code? Is hdl code specific to a particular board or chip like say iCE40? | 12:56 |
| zyp | depends whether the code is instancing primitives that only exists in a particular chip or not | 12:57 |
| lambda | "it depends" - the main logic of any design will probably be pretty generic, but especially when it comes to IOs, you often need to manually instantiate your device's primitives | 12:58 |
| infinite_recursi | By instancing primitives, do you mean functions specific to an fpga board? | 12:58 |
| infinite_recursi | ok | 12:59 |
| infinite_recursi | I guess I'll learn this when I do things. | 12:59 |
| lambda | no, hard logic blocks inside the chip - things like PLLs, SERDES, etc | 12:59 |
| zyp | if you're familiar with microcontrollers, it's analogous to how some code is accessing hardware registers present in a specific chip, while other code might be compiled for any chip | 12:59 |
| infinite_recursi | Yes, got it. Thank you lambda and zyp! :D | 13:00 |
| zyp | so in practice you often end up with some files of portable code along with some «glue» code to help it work on a particular chip | 13:02 |
| zyp | and by replacing the glue code, you can build it for different targets | 13:02 |
| infinite_recursi | Would the glue code be long enough or some big structure changes or it would just be some minor edits? | 13:07 |
| infinite_recursi | And would I have to take care about it while structuring code? | 13:07 |
| lambda | infinite_recursi: if you want to simulate your code, it may just come naturally if there are no simulation models for the primitives you're using, so you'll have to stub them out anyway :) | 13:14 |
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| infinite_recursi | ok. | 13:24 |
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| -_whitenotifier- [prjxray] tmichalak opened issue #1546: Add baseaddresses for GTPE2_CHANNEL sites - https://git.io/JtJEM | 15:11 | |
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| umarcor | schris15: what's your preference? HDL, Docker, Python or C++? All of them? Do you want to work on hardware designs or on tooling for hadware design? | 17:47 |
| sf-slack | <schris15> I only have around 6weeks of FPGA design experience with even less being on HDL, so unless its something simple I would prefer python. | 17:49 |
| umarcor | @infinite_recursi, you might want to have a look at https://workshop.fomu.im. Very precisely https://workshop.fomu.im/en/latest/background.html and 'Turning code into gates'. That's not the most exhaustive explanation, but it will let you find yourself. | 17:50 |
| tpb | Title: Background FPGA Tomu (Fomu) Workshop 0.1-320-gd1e14dc documentation (at workshop.fomu.im) | 17:50 |
| sf-slack | <schris15> ok thank you | 17:50 |
| umarcor | schris15, that second message of mine was for another user. However, you might also want to read the workshop. You will already know most of that, but it's always interesting to read a different point of view. | 17:53 |
| sf-slack | <schris15> oh yeah i didn't notice | 17:54 |
| sf-slack | <schris15> yeah i'm familiar with those | 17:54 |
| umarcor | Then, if you are comfortable with Python, I would recommend two working areas: | 17:55 |
| umarcor | 1. HDL generators | embedded HDL languages, such as migen/nmigen. That will allow you to do hardware design without learning Verilog/VHDL specifics. Not my cup of tea, but very used in the open source community. Search e.g. litex-hub on GitHub. | 17:55 |
| infinite_recursi | umarcor: Thanks, read it. It's fomu specific but helped. | 17:57 |
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| umarcor | 2. HDL project packagers|managers, such as edalize/fusesoc, PyFPGA, tsfpga, pyIPCMI, cheby, hdlmake... All of those are written in Python. All of them need love, and any integration effort would be delightful for the community. | 17:58 |
| cr1901_modern | What is cheby? A filter maker? | 17:58 |
| sf-slack | <schris15> ok thanks for the info, i will take a look | 17:59 |
| umarcor | 2. (bis) Tool packagers|managers for easily distributing and installing environments. Antmicro/SymbiFlow is focused on Conda for that, which is Python. Again, not my cup of tea (I'm not very fond of Python's packaging environments), but it has traction. | 17:59 |
| umarcor | cr1901_modern: https://gitlab.cern.ch/cohtdrivers/cheby It's for HW/SW interfaces. It generates files for hardware and for software to match. I believe that tsfpga and other projects have similar built-in features. | 18:00 |
| tpb | Title: Projects · cohtdrivers / cheby · GitLab (at gitlab.cern.ch) | 18:00 |
| umarcor | I think that cheby is based on Wishbone, but I cannot confirm that. | 18:01 |
| umarcor | I'm aware of it because the main author is also the author of GHDL. | 18:02 |
| cr1901_modern | ahhh | 18:02 |
| umarcor | cr1901_modern: you might want to have a look at the following docs: | 18:05 |
| umarcor | about packaging and project management for simulation and/or synthesis: https://docs.google.com/document/d/1qThGGqSVQabts-4imn5zY5BMptp1-Q2rGiNKHDH1Pbk | 18:06 |
| tpb | Title: EDA integration: managing projects for simulation and implementation - Google Docs (at docs.google.com) | 18:06 |
| umarcor | with regard to building and distributing tools: https://docs.google.com/document/d/10_MqFjTIYVVuOJlusJydsp4KOcmrrHk03__7ME5thOI/ | 18:06 |
| tpb | Title: Open Source EDA: building, packaging, installing - Google Docs (at docs.google.com) | 18:06 |
| umarcor | infinite_recursi: related to managing HDL projects targeting multiple boards/FPGA, I would suggest to have a look at https://github.com/dbhi/vboard/tree/main/vga, precisely https://github.com/dbhi/vboard/tree/main/vga#how-to-add-a-board. | 18:11 |
| umarcor | That is a "traditional" approach for VHDL/Verilog designs, using makefiles only. The repository was created as an example of how to organise sources (src, board, device, test...) for newcomers to have a reference about how to structure their code, and avoid later refactorisations. | 18:11 |
| umarcor | However, there are "higher level" approaches to the problem. Fusesoc is one of them, which uses `.core` files. LiteX has a litex-boards repository, which contains the same infor as hdl/constraints, but embedded in a Python tool. | 18:13 |
| umarcor | In fact, one of the main inspirations for the structure was https://github.com/PLC2/Solution-StopWatch. PLC2 is a german HDL training company, which organises FPGA Kongress. | 18:15 |
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| mithro | @litghost is https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1608 ready to merge? | 18:57 |
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| sf-slack | <kgugala> @mithro @litghost this change https://github.com/SymbiFlow/prjxray/pull/1539/commits/082e98291177fc8194ac71b1680641df119476e7#diff-4f8a3806dcb8d938999[…]318fd2c997d4e5de2f082dR64 implicitly introduces db/mapping/devices.yaml file requirement for xc7-fasm. We need to publish new database with this file, otherwise binary toolchain is crashing | 21:26 |
| litghost | True... | 21:27 |
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| litghost | We really need to not having endpoint users using bleeding edge | 21:32 |
| sf-slack | <kgugala> yep - we need to fix the package on certain commit | 21:33 |
| sf-slack | <kgugala> doing this in the examples repo should be fine (as it is our official user guide) | 21:34 |
| sf-slack | <kgugala> and the docs are generated from it | 21:34 |
| litghost | I'm not convienced about using commit, rather than package versions | 21:43 |
| litghost | for Python packages | 21:43 |
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| sf-slack | <kgugala> I don't think we publish prjxray python package (I agree this will be better than pointing to a commit) | 21:44 |
| litghost | We need to get PyPI publishing started, biggest issue I see is that PyPI doesn't really have a "organization" concept, just an owning account | 21:46 |
| sf-slack | <kgugala> yep | 21:46 |
| sf-slack | <kgugala> I opened PR hotfixing the prjxray version https://github.com/SymbiFlow/symbiflow-examples/pull/117 | 21:49 |
| sf-slack | <kgugala> Once we have a proper python package we should reverse this | 21:49 |
| litghost | We'll also want to bump it once the new db is propigated | 21:50 |
| sf-slack | <kgugala> yep | 21:50 |
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