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| cjearls | I know I can't just throw it on and tie the signals to 0 because most of the logic will be optimized away, so I'm looking for a way to prevent this. If it's not possible to prevent, how can I configure the pins on my FPGA? For reference, I am using an orangecrab board | 00:01 |
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| umarcor|2 | @HackerFoo, @litghost, you might find https://ghdl.github.io/ghdl-cosim/vhpidirect/examples/shared.html interesting. | 01:33 |
| tpb | Title: Shared libs and dynamic loading GHDL-cosim latest documentation (at ghdl.github.io) | 01:33 |
| umarcor|2 | That's about loading shared libraries in Python, (re)defining some functions/variables and then using them from VHDL. | 01:34 |
| Lofty | cjearls: nextpnr-ecp5 has an option for "out of context" mode, which just ignores the I/O pins | 01:35 |
| umarcor|2 | https://bugs.python.org/issue41348 | 01:36 |
| tpb | Title: Issue 41348: Support replacing global function pointers in a shared library - Python tracker (at bugs.python.org) | 01:36 |
| Lofty | (it's designed for blocks to be placed and routed to be used for other things) | 01:36 |
| HackerFoo | umarcor|2: Thanks | 01:36 |
| umarcor|2 | You can ignore the VHDL part, of course. The point is that ctypes allows interacting with any language that understands C prototypes, not only C/C++. | 01:38 |
| umarcor|2 | And, as you said, it's built in Python, so no additional deps are required. | 01:39 |
| cjearls | Lofty: So I can just use my design as the top Verilog file and use "out of context" mode and everything should just work? Is there anything else I need to do? | 01:39 |
| Lofty | Nope, that's it. | 01:39 |
| Lofty | You can use things like pack or place only to get faster but less accurate answers | 01:40 |
| Lofty | It is entirely possible to have a design which fits neatly into the chip but is not routable, though, so keep that in mind | 01:41 |
| Lofty | In my experience nextpnr is fast enough that it's generally easy to go through the whole cycle | 01:41 |
| Lofty | cjearls: oh, and you're building with 'synth_ecp5 -abc9' right? | 01:43 |
| cjearls | Not currently, the command I was going to run was "nextpnr-ecp5 --25k --out-of-context" | 01:44 |
| cjearls | Lofty: How should my directory be set up? Are there any other arguments I need? | 01:47 |
| Lofty | Well, you need the --json, but other than that, no; the defaults are fine | 01:48 |
| Lofty | And nextpnr doesn't really do much to a directory (which is good) | 01:48 |
| Lofty | So it doesn't matter | 01:49 |
| cjearls | Lofty: I've never run Symbiflow on its own without a premade script before | 01:49 |
| cjearls | So I need to call yosys, then nextpnr, correct? | 01:49 |
| umarcor|2 | cjearls, are you familiar with makefiles? | 01:49 |
| cjearls | umarcor|2: Yes | 01:50 |
| umarcor|2 | Here you are: https://github.com/antonblanchard/ghdl-yosys-blink | 01:50 |
| umarcor|2 | That's a blink example for the orangecrab using a makefile. | 01:50 |
| Lofty | `yosys -p "synth_ecp5 -abc9 -json netlist.json" <Verilog files>; nextpnr-ecp5 --25k --out-of-context --json netlist.json` | 01:50 |
| umarcor|2 | There you can see yosys + nextpnr + ecppack | 01:51 |
| cjearls | umarcor|2: Thank you, Highly appreciated | 01:51 |
| cjearls | Lofty: Thank you as well | 01:51 |
| umarcor|2 | You need to adapt it to the guidelines that Lofty provided, tho | 01:51 |
| Lofty | umarcor|2: but that's... not what was asked for | 01:51 |
| cjearls | I'm new to most of this, so if it's entirely possible that I'm not asking for the right things | 01:52 |
| umarcor|2 | Lofty, I'm providing it for him/her to understand the steps involved in generating a bitstream from HDL sources: synthesis, implementation and packaging. | 01:52 |
| Lofty | Either way: the number one way you can improve the quality of result of Yosys for ECP5 is that magic '-abc9' option | 01:53 |
| cjearls | Very interesting, I wonder what that does | 01:53 |
| Lofty | https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md (for all the synth_ecp5 options) | 01:54 |
| cjearls | It looks like it sets the ABC logic synthesis tool to 9, which I guess is the maximum optimization level | 01:54 |
| Lofty | https://github.com/Ravenslofty/yosys-cookbook/blob/master/misc/abc9.md (for -abc9 specifically) | 01:54 |
| Lofty | cjearls: hah, no. It's ABC v9 :P | 01:55 |
| cjearls | RIP, I tried | 01:55 |
| cjearls | Lofty: Thanks for the clarification | 01:55 |
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| Lofty | Well, the way things are going, it's going to be my job to improve docs there | 01:56 |
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| Lofty | After I wrote something that beats ABC, anyway :P | 01:58 |
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| -_whitenotifier-f- [fpga-interchange-constraints] litghost opened issue #4: The current "at most one" encoding is not optimal - https://git.io/JkCrQ | 02:03 | |
| cjearls | Lofty: Has anyone done any comparisons of the utilization or clock speeds of Symbiflow vs the manufacturer tools? | 02:03 |
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| Lofty | Not specifically for ECP5 | 02:04 |
| Lofty | https://github.com/symbiflow/fpga-tool-perf tries to do this in general, but yeah | 02:04 |
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| Lofty | There's kind of a -O3 type mode for ABC9, but it's a bit of a mess | 02:09 |
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| Lofty | (anyway, I'm going to sleep, it's 2am) | 02:19 |
| cjearls | Lofty: Thanks for your help, very much appreciated | 02:19 |
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| cjearls | When I run yosys, It runs for a while, then says "Terminated" but doesn't generate the netlist.json | 03:40 |
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| -_whitenotifier-f- [symbiflow-arch-defs] the-centry opened issue #1779: Why the kintex7'db - https://git.io/JkWTh | 07:15 | |
| -_whitenotifier-f- [symbiflow-arch-defs] the-centry opened issue #1780: Why the kintex7'dbs exist in prjxray-db but the symbiflow can't use k7's device? - https://git.io/JkWkj | 07:27 | |
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| sf-slack4 | <olof.kindgren> @cjearls: You might be interested in Edalize. That will generate the project files for any of the 25 EDA tool flows currently supported | 08:42 |
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| -_whitenotifier-f- [fpga-tool-perf] acomodi opened issue #271: Daisho USB design failing - https://git.io/JklkZ | 14:49 | |
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| -_whitenotifier-f- [fpga-tool-perf] acomodi opened issue #272: Create error codes to get more information on build statuses - https://git.io/JklYc | 15:21 | |
| cjearls | @olof.kindgren Thanks for the recommendation | 15:57 |
| cjearls | I ran the netlist that gets "Terminated" with some smaller hardware and it ran fine, so seems like my design was too big for the board | 15:57 |
| -_whitenotifier-f- [fpga-tool-perf] mithro opened issue #273: Integrate build result publishing - https://git.io/Jklum | 16:46 | |
| sf-slack4 | <olof.kindgren> @cjearls: And if you want to know more about Edalize I can recomment the award-winning introduction video | 17:02 |
| Lofty | You can't just keep giving yourself awards, olof :P | 17:12 |
| sf-slack4 | <olof.kindgren> @lofty: But, but... that's the only way I will get any awards!?! | 17:33 |
| Lofty | :P | 17:33 |
| -_whitenotifier-f- [symbiflow-arch-defs] litghost opened issue #1783: Remove `VTR + symbiflow-arch-defs` step from arch-defs builds - https://git.io/JkloG | 17:43 | |
| -_whitenotifier-f- [conda-packages] HackerFoo opened issue #144: CI fails on forks if user doesn't have their own channel at conda.anaconda.org - https://git.io/JklMA | 19:08 | |
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