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| umarcor | kd2cca: for VHDL, https://github.com/Paebbels/sphinxcontrib-vhdldomain; and for Verilog, https://github.com/SymbiFlow/sphinx-verilog-domain. Both are WIP (alpha), AFAIU. | 00:39 |
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| umarcor | See also the 'Documenter' section of TerosHDL (https://github.com/TerosTechnology/vscode-terosHDL#id6): wavedrom support, bitfields, etc. | 00:42 |
| sf-slack4 | <kd2cca> oooo chachacha. Last time i looked it was just flow charts. | 01:12 |
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| -_whitenotifier-f- [sv-tests] caryr opened issue #1143: Error in test code - https://git.io/JkGIF | 06:26 | |
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| sf-slack4 | <olof.kindgren> Ok, I'm starting to become pretty sure that bitstream_to_header script is wrong | 20:57 |
| sf-slack4 | <olof.kindgren> Or maybe not... | 21:14 |
| sf-slack4 | <olof.kindgren> So, here's what I observer. I preload a 32-bit word to a memory during synthesis. On the board I read back word 0. It looks like the lower 16 bits are all fine, but that the highest 16 bits correspond to the last word in the `axFPGAMemInit` array. Could it be something stupid like the memInit function reads the top half backwards or something? | 21:16 |
| sf-slack4 | <olof.kindgren> Don't think I will get any further with this but hopefully enough for someone to find out where things go wrong | 21:20 |
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