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| sf-slack4 | <tpagarani> @olof.kindgren, Looks like you were able to figure out the memory init routines. The reason data has been split and bits are shuffled is because of the internal memory organization. Our internal physical memory block is actually each 18K which can be used as single 18K or 2 independent 9K blocks. In 18K mode, it can be configured as 2048x9, 1024x18 OR 512x36. In 9K mode it can be configured as 1024x9 OR 512x18. | 03:05 |
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| sf-slack4 | For Synthesis, we are only currently supporting x8, x16, x32 data widths (other bits are meant for parity which we don't support yet). That's why you would see that your data is being padded with parity bit set to 0. | 03:05 |
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| sf-slack4 | <olof.kindgren> @tpagarani Cool. I kind of guessed it had to do with internal layout but wanted to make sure it wasn't something wrong. Good to get that confirmed | 07:56 |
| sf-slack4 | <tpagarani> @olof.kindgren, Please share your project with output files as well. I will confirm if RAM init sections look okay. | 08:56 |
| sf-slack4 | <olof.kindgren> @tpagarani Here's the source and build for the .bit file. The source of the memory init data is in the file blinky.hex | 09:11 |
| sf-slack4 | <olof.kindgren> This is built outside of qorc-sdk, and after I have built the FPGA image, I copy the bit file + ram.mem into the qf_helloworldhw project and regenerate. | 09:12 |
| sf-slack4 | <olof.kindgren> So which files from the qf_helloworldhw project do you need? All of them? | 09:12 |
| sf-slack4 | <olof.kindgren> Or just the elf file and , _bit.h file ? | 09:13 |
| sf-slack4 | <olof.kindgren> Here's the whole project | 09:15 |
| sf-slack4 | <tpagarani> @olof.kindgren you should be able to generate the header file within symbiflow itself rather than taking bit + ram.mem info qf_hellowordw project. https://quicklogic-fpga-tool-docs.readthedocs.io/en/latest/tutorial/GeneratetheASCIIheaderfilef.html | 09:20 |
| tpb | Title: Generate the ASCII header file format QuickLogic-FPGA-Toolchain (at quicklogic-fpga-tool-docs.readthedocs.io) | 09:20 |
| sf-slack4 | <olof.kindgren> Ah, cool. Then I only need to add the h file to the project. Need to chek if the edalize backend supports passing custom options to the symbiflow commands to do that | 09:29 |
| sf-slack4 | <olof.kindgren> Hm.. need to check which commands this ql_symbiflow script runs | 09:31 |
| sf-slack4 | <olof.kindgren> ah, ok. It calls the bitstream_to_header.py script eventually. That python script is a bit awkward since it relies on having files in certain directories | 09:35 |
| sf-slack4 | <olof.kindgren> So it might be easier for now to just make a modified version of that script and add it as an Edalize post_build hook for now | 09:36 |
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| mithro | litghost: How does https://github.com/SymbiFlow/prjxray-db/compare/master...mithro:master look? | 18:06 |
| litghost | mithro: Looks like that incorporates the expected changes | 18:19 |
| mithro | litghost: Do you have any info on https://github.com/SymbiFlow/fpga-tool-perf/issues/262 ? | 18:20 |
| litghost | mithro: I posted https://github.com/SymbiFlow/fpga-tool-perf/issues/262#issuecomment-721224923 and stand by the comment | 18:21 |
| litghost | mithro: The missing bit specifically is trying to route a clock from the interconnect to the OSERDES (I believe). While the database should have that bit, it is a bad sign if the router is trying to route a clock on the interconnect at all. | 18:22 |
| litghost | mithro: In the past that kind of routing was the result of a stray INV cell being between the clock and the Cell | 18:22 |
| mithro | litghost: The issue at https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1750 is a seperate issue too? | 18:23 |
| litghost | mithro: ISERDES and OSERDES usually have local inverters that are strongly preferred over implementing the inversion as a INV -> LUT1 cell | 18:23 |
| litghost | mithro: Some of those bits are "easy", per mkurc's comment here: https://github.com/SymbiFlow/symbiflow-arch-defs/issues/1750#issuecomment-721689430 | 18:23 |
| litghost | mithro: The GTP_COMMON_MID_RIGHT bits haven't been relevant to date, so no one stood up a fuzzer | 18:24 |
| litghost | mithro: The easiest solution to both of these issues to exclude the PLL in the CMT with the GTP from being used, as it has some stranger routing. | 18:25 |
| mithro | HackerFoo: See the above discussion | 18:25 |
| litghost | mithro: In earlier demostrations of ibex on 200T, we used a graph limit to exclude the portion of the fabric that we were missing bits | 18:25 |
| litghost | mithro: Given the low number of pips missing, it is likely that standing up a GTP_COMMON_MID_RIGHT fuzzer wouldn't be too bad, and updated 034b to capture the REBUF pips is also possible | 18:26 |
| HackerFoo | mithro: Thanks | 18:28 |
| -_whitenotifier-f- [prjxray] mithro opened issue #1493: Database HTML generation output on prjxray-db push failing - https://git.io/JkOtM | 18:37 | |
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| -_whitenotifier-f- [symbiflow-arch-defs] HackerFoo opened issue #1773: Use VPR's RR graph node reordering and remove hilbertcurve dependency - https://git.io/JkOqi | 18:47 | |
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| mithro | @litghost / @mkurc: New prjxray-db pushed | 18:52 |
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| sf-slack4 | <mkurc> @litghost I may have a solution for ISERDES/OSERDES clock inverters that come as a result of connecting clocks like `.CLK(~my_clk)` in verilog. Some time ago I wrote a Yosys plugin that integrates inverter cells into hard blocks that have invertible pins. It works in the opposite way as the built-in pass `extractinv`. If that could be helpful I can clean up the code and make a PR in the upcoming week. | 21:30 |
| litghost | mkurc: That's what I expected. I believe yosys has a way to deal with invertable clocks already. | 21:30 |
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| sf-slack4 | <olof.kindgren> I'm trying to verify the contents of the first memory position by guessing each bit position and turning on a LED if it's correct. 8 done, 24 left. Sometimes I wonder if I should invest in better debugging solutions :) | 22:05 |
| sf-slack4 | <olof.kindgren> So to clarify, I rebuild the bitstream between every attempt | 22:05 |
| sf-slack4 | <olof.kindgren> It's a bit weird. I expect it to be 0x40000357, but that test fails. However, I have uncovered that the 8 LSB are 0x57, so I'm very curious to see where it goes wrong | 22:07 |
| sf-slack4 | <olof.kindgren> Doing a leap of faith now and testing 4 bits at the same time to hopefully speed up the process | 22:08 |
| sf-slack4 | <olof.kindgren> Yes! 12 bits done | 22:09 |
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| sf-slack4 | <olof.kindgren> ok, so bit 30 is not correct. Should be 1. Is 0 | 22:44 |
| sf-slack4 | <olof.kindgren> I wonder if there's some bit shuffling problem in the init file generation going on. Let's see what bit 31 is | 22:44 |
| sf-slack4 | <olof.kindgren> But that's also the only 1 in the top 16 bits of the word, so theoretically, it could be that the whole upper halft is 0. Will need some further investigation | 22:46 |
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| sf-slack4 | <olof.kindgren> Right, so I have confirmed that 0x40000537 becomes 0x00000537 in the device. Question now is where things go wrong | 22:56 |
| sf-slack4 | <olof.kindgren> So I did an experiment where I set bit 16 as well, so that my complete word becomes 0x40010537 and compared to 0x00010537. This failed as well. Working theories now is that the top half is not working correctly or that the parity bits get messed up with the data | 23:11 |
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| sf-slack4 | <olof.kindgren> I give up for now, but something is definitely wrong here and I guess someone else than me is better suited for figuring out what is wrong | 23:14 |
| sf-slack4 | <olof.kindgren> ok, one last result. I checked the 17 lowest bits against {1'b1,16'h0537} and that failed as well, so I'm getting increasingly convinced there's some problem with the whole upper 16 bits | 23:19 |
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