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| -_whitenotifier-f- [prjxray] the-centry opened issue #1485: where the ignored wires in 074 are from - https://git.io/JTAxP | 05:48 | |
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| sf-slack | <mkurc> @mithro Thanks | 07:59 |
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| -_whitenotifier-f- [sv-tests] tgorochowik opened issue #1127: The installed yosys package is obsolete - https://git.io/JTxZD | 10:35 | |
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| ptll | \prjxray-db-master\kintex7\segbits_int_l.db | 15:06 |
| ptll | 1. This reference file is based on which tile, ie what is the i & j of the tile INT_L_XiYj ? | 15:06 |
| ptll | 2. If the reference tile is known, how do we find the bitstream location of similar pips in another tile eg INT_L_X(i+m)Y(j+n) ? | 15:06 |
| ptll | 3. If the reference tile is known, how do we find the bitstream location of similar pips in the same tile INT_L_XiYj of another kintex7 FPGA | 15:07 |
| ptll | 4. In prjxray notation, do frame numbers start at 0 or 1? | 15:07 |
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| litghost | ptll: In general, you can just use bit2fasm to handle processing a bitstream into FASM features | 17:36 |
| litghost | ptll: If you want more details, you can checkout https://symbiflow.readthedocs.io/projects/prjxray/en/latest/ and https://github.com/SymbiFlow/prjxray/blob/master/prjxray/fasm_disassembler.py and https://github.com/SymbiFlow/prjxray/blob/master/prjxray/fasm_assembler.py | 17:37 |
| tpb | Title: Project X-Ray Project X-Ray 0.0-3287-g780b7e4d documentation (at symbiflow.readthedocs.io) | 17:37 |
| litghost | https://github.com/SymbiFlow/prjxray/blob/master/utils/bit2fasm.py | 17:38 |
| sf-slack | <alberto.anzellotti> Hello everyone! I'm a physics student and have no previous experience with FPGAs. At the moment I'm working with portable spectrometers, AI and Adalm Pluto SDR. I'm interested in understanding what an FPGA is capable of in terms of signal processing/filtering and maybe AI. Where should I start from? I WANT my designs to be open source! :) (and I know python and electronics) is this a good start? | 17:40 |
| sf-slack | https://www.amazon.it/Digilent-319-Arty-artix-7-FPGA-sviluppo-piattaforma/dp/B07D1DVRG6/ref=sr_1_1?__mk_it_IT=%C3%85M%C3%85%C5%BD%C3%95%C3%91&dchild=1&keywords=arty+a7&qid=1604597361&quartzVehicle=5-112&replacementKeywords=arty&sr=8-1 Or am I better off with an Alchitry AU? Thanks! | 17:40 |
| litghost | mithro posted this a couple days ago, which is relevant: https://twitter.com/assortedhackery/status/1317849554629296129 | 17:43 |
| litghost | There have been a plethora of SDR boards in the last couple years with FPGAs + frontends. For example the BladeRF folks make boards with Altera Cyclone V FPGAs | 17:47 |
| litghost | The Arty board you linked does have an FPGA, but it lacks an RF front end (e.g. tuning/DAC/ADC). | 17:50 |
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| sf-slack | <coreyrsimpson> Hello, I am a graduate student at BYU, I am currently looking to contribute to the prjxray series 7 database. I'm specifically looking at the DSP database, and from conversations I have heard that the DSP segibts aren't complete. I see that fuzzer 100-dsp-mskpat solves for many of the features associated with the DSP, is the DSP_L/R tiles complete? By inspection, the only features I can identify that aren't in | 18:40 |
| sf-slack | the database is the USE_MULT attribute with "NONE", "DYNAMIC" and "MULTIPLY". | 18:40 |
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| sf-slack | <alberto.anzellotti> sure, but Arty is compatible with symbiflow, Altera is not. Am I right? The Adalm Pluto I own, already has a Xilinx Zynq Z-7010 containing a small FPGA. There should be enough room left on this FPGA to link it to a secondary external FPGA like the one I mentioned... would that be possible? | 22:02 |
| sf-slack | <alberto.anzellotti> sure, but Arty is compatible with symbiflow, Altera is not. Am I right? The Adalm Pluto I own, already has a Xilinx Zynq Z-7010 containing a small FPGA. There should be enough room left on this FPGA to link it to a secondary external FPGA like the one I mentioned... would that be possible? | 22:02 |
| daveshah | coreyrsimpson: iirc when I last looked at DSPs, there were some cascade bits missing | 22:04 |
| daveshah | USE_MULT didn't affect the bitstream, I think its mainly for power and maybe timing analysis usage | 22:04 |
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| litghost | I was googling around, and it looks like the KiwiSDR uses an artix7, but I cannot speak at all about the rf qualities of that board | 22:55 |
| litghost | Seeedstudio are usually pretty good about providing schematics, so that is an option. | 22:55 |
| litghost | The artix7 in that board is the 35t, which is the smallest artix7 part. | 22:57 |
| litghost | Also looks like the FreeSRP uses an artix7 | 23:02 |
| litghost | FreeSRP is using a A100T which is the middle sized part in the artix7 series | 23:03 |
| litghost | To date we have not tried to place and route SDR type designs. Might be good to try synth + place and route of those designs and see if we close timing. I suspect it might not, but always good to get more circuits going | 23:05 |
| litghost | Nevermind on FreeSRP, looks like that didn't get off the ground. | 23:11 |
| sf-slack | <alberto.anzellotti> @litghost the FreeSRP looks like it would be a great platform, but it's not available anywhere! | 23:12 |
| sf-slack | <alberto.anzellotti> KiwiSDR is RX only | 23:12 |
| sf-slack | <alberto.anzellotti> Adalm Pluto is cheap, has a Xilinx Zynq, is widely available and has both rx and tx. Only issue, that Zynq FPGA sounds small. Can a softCPU fit in the Xilinx Zynq Z-7010? | 23:14 |
| litghost | The zynq fabric has an arm core right on the fabric | 23:15 |
| litghost | So I don't know why you'd soft core in that case | 23:15 |
| litghost | But yes, a soft core is possible | 23:15 |
| litghost | We demo'd a linux capable SoC on zynq using the arm cores ddr as the memory controller | 23:16 |
| litghost | Not sure if it was the 7010 or 7020 though | 23:16 |
| sf-slack | <alberto.anzellotti> that's true, just to mess around and start learning FPGA the easy way... after that I'd like to implement a tunable bandpass filter on the FPGA. | 23:17 |
| sf-slack | <alberto.anzellotti> "We demo'd a linux capable SoC on zynq using the arm cores ddr as the memory controller"- Cool! Do you have a link? | 23:17 |
| litghost | sure, that is totally doable | 23:17 |
| litghost | @kgulala did that I believe | 23:18 |
| sf-slack | <alberto.anzellotti> @litghost Awesome! Thanks! I hope @kgugala can point me in the right direction! :) | 23:21 |
| litghost | We have been meaning to add zynq examples on symbiflow-examples, so that might be a good candidate once a counter type design is up | 23:22 |
| sf-slack | <olof.kindgren> @alberto.anzellotti Have you looked at pyfda. It's a filter toolbox that cam spit out HDL. Haven't tried it myself but heard good things about it. | 23:31 |
| sf-slack | <coreyrsimpson> Daveshah, as far as cascade dsp bits go, are you referring to the pips that connect dsps that are next to each other, and those are the ones not solved for, or what are you referring to? As far as within the dsp48e1 site type, I can't find any other features that I would expect to exist that prjxray hasn't already documented | 23:35 |
| sf-slack | <alberto.anzellotti> Wow! Thanks! I didn't know about it! Looks amazing! | 23:38 |
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