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| mithro | thestorageguy: It's Xilinx not Xylinx | 00:49 |
|---|---|---|
| mithro | Lofty / umarcor: the Quartus -> VQM -> BLIF -> VPR flow was about allowing VPR to work on more "real world designs" given the lack of support for many constructs / languages / etc in ODIN-II / Yosys (specially back in 2014 when it was first released) -- See https://www.eecg.utoronto.ca/~kmurray/titan.html for a complete discussion. It is also what heavily drove VPR's support for SDC and other timing constraints and | 01:05 |
| mithro | multi-clock support. | 01:05 |
| tpb | Title: Titan (at www.eecg.utoronto.ca) | 01:05 |
| mithro | There is work to have a similar set of Yosys -> BLIF -> VPR benchmarks for Xilinx 7 series and Ultrascale | 01:07 |
| mithro | Back in 2014, the capabilities of VPR place and route were significantly past the capabilities of the open source synthesis flow -- wasn't until 2015-03-22 that Project IceStorm was first released. | 01:09 |
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| sf-slack | <thestorageguy> I found this project https://github.com/SymbiFlow/prjuray | 05:53 |
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